VT8601 Via, VT8601 Datasheet - Page 52

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Device 0 Offset 75 - PCI Arbitration 1 ............................ RW
Revision 1.3 September 8, 1999
5-4
3-0
7
6
7HFKQRORJLHV ,QF
Arbitration Mechanism
Arbitration Mode
Latency Timer ........... read only, reads Rx0D bits 2:1
PCI Master Bus Time-Out
(force into arbitration after a period of time)
:H &
:H &R R QQHFW
0000 Disable ...................................................default
0001 1x32 PCLKs
0010 2x32 PCLKs
0011 3x32 PCLKs
0100 4x32 PCLKs
1111 15x32 PCLKs
... ...
0
1
0
1
QQHFW
PCI has priority ......................................default
Fair arbitration between PCI and CPU
REQ-based (arbitrate at end of REQ#)...default
Frame-based (arbitrate at FRAME# assertion)
-46-
Device 0 Offset 76 - PCI Arbitration 2 ............................ RW
Device 0 Offset 77 - Chip Test Mode ............................... RW
5-4
3-2
7-6
5-0
7
6
1
0
CPU-to-PCI Post-Write Retry Failed
CPU Latency Timer Bit-0 ....................................RO
Master Priority Rotation Control
With setting 01, the CPU will always be granted
access after the current bus master completes, no
matter how many PCI masters are requesting. With
setting 10, if other PCI masters are requesting during
the current PCI master grant, the highest priority
master will get the bus after the current master
completes, but the CPU will be guaranteed to get the
bus after that master completes. With setting 11, if
other PCI masters are requesting, the highest priority
will get the bus next, then the next highest priority
will get the bus, then the CPU will get the bus. In
other words, with the above settings, even if multiple
PCI masters are continuously requesting the bus, the
CPU is guaranteed to get access after every master
grant (01), after every other master grant (10) or after
every third master grant (11).
High Priority REQ Select
CPU-to-PCI QW High DW Read Access to PCI
Slave Allow Backoff
High Priority Request Support
Reserved (no function) ....................... always reads 0
Reserved (do not use) .................................default=0
00 Disabled (arbitration per Rx75 bit-7)..... default
01 Grant to CPU after every PCI master grant
10 Grant to CPU after every 2 PCI master grants
11 Grant to CPU after every 3 PCI master grants
00 REQ4 .................................................... default
01 REQ0
10 REQ1
11 REQ2
0
1
0
1
0
1
0
1
Continue retry attempt ........................... default
Go to arbitration
CPU has at least 1 PCLK time slot when CPU
has PCI bus ............................................ default
CPU has no time slot
Disable................................................... default
Enable
Disable................................................... default
Enable
Device 0 Bus 0 Host Bridge Registers
VT8601 Apollo ProMedia