VT8601 Via, VT8601 Datasheet - Page 93

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

GR23 – Power Status ........................................................ RW
Revision 1.3 September 8, 1999
6-5
3-2
1-0
7
4
7HFKQRORJLHV ,QF
Power Management Pin Polarity (see GR21[7])
Chip Power Status
LCD Power Sequence Status
Panel Power Sequencing
DPMS Power Status
In hardware mode, these bits indicate the status of
CRT Hsync and Vsync as well as the internal
RAMDAC power state (the “off” mode state can be
read only in CRT only mode). In software mode,
these bits control the state of the CRT Hsync and
Vsync signals but not the power state of the internal
RAMDAC.
power state of the RAMDAC is not controlled by the
DPMS Power State (bits 1-0), but by the Chip Power
State (bits 6-5).
:H &
:H &R R QQHFW
00 Ready
01 Standby
10 Suspend
11 -reserved-
00 Fast panel power sequencing..................default
01 -reserved-
10 -reserved-
11 Slow panel power sequencing
00 On Mode (CRT interface is active and
01 Standby Mode (Hsync disabled, Vsync active,
10 Suspend Mode (Vsync disabled, Hsync active,
11 Off Mode (Hsync and Vsync disabled, DAC
0
1
QQHFW
LCD power sequencing is not occurring at this
time
LCD power sequencing is occurring at this
time
RAMDAC is full on) ..............................default
DAC off, RAMDAC color palette lookup
table (LUT) video data path is off but LUT
I/O is allowed)
RAMDAC is off but contents are retained)
LUT is full off)
In simultaneous display modes, the
-87
GR24 – Software Power Control ..................................... RW
GR25 – Power Control Select .......................................... RW
When any of bits 7-6 or 3-0 are set to 1, the corresponding
power control bit reads back the logic state of the internal
power management engine.
hardware power control and 1 selects software power control.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VCLK
MCLK
CPU & DRAM Data Bus
Reserved
ENPBLT
Control
Software Power Control
Hardware Power Control (timers, pin, register bit)
Panel VDD
Panel Interface Signals
Panel VEE
Power Control for VCLK .............................. def = 1
Power Control for MCLK ............................ def = 1
Power Control for the Data Bus ................... def = 1
Power Control for the RAMDAC ................ def = 1
The RAMDAC is software enabled in GR26[7-6]
Power Control for Panel Enable / Backlight def = 1
(see GR24[3])
Power Control for Panel VDD .....................def = 1
Power Control for Panel Interface Signals .def = 1
Power Control for Panel VEE ......................def = 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disable
Enable................................................... default
Disable
Enable................................................... default
Disable
Enable................................................... default
Drive ENPBLT Low.............................. default
Drive ENPBLT High
ENPBLT is active low........................... default
ENPBLT is active high
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
(Panel
........................................ always reads 0
VT8601 Apollo ProMedia
and/or
For all bits below, 0 selects
VGA Extended Registers
Backlight
Enable)