VT8601 Via, VT8601 Datasheet - Page 22

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Signal Name
MD[63:0]
MA[14:0]
/ Strap Options
CKE5# / SRASB#,
CKE4# / SRASC#,
CKE3# / SCASB#,
CKE2# / SWEB#,
CKE1# / SCASC#,
CKE0# / SWEC#
RAS[5-0]# / CS[5-0]#
CAS#[7:0] / DQM[7:0]
SRASA#,
SRASB# / CKE5,
SRASC# / CKE4
SCASA#,
SCASB# / CKE3
SCASC# / CKE1
SWEA# / MWEA#,
SWEB# / MWEB# / CKE2,
SWEC# / MWEC# / CKE0
Note: Clocking of the memory subsystem uses memory clock (MCLK); see the clock pin group at the end of the pin descriptions
Note: Connect all memory interface pins except MD to the DRAM modules through 22 series resistors (see the Apollo ProMedia
Revision 1.3 September 8, 1999
7HFKQRORJLHV ,QF
section for descriptions of the clock pins.
Design Guide” for more specific connection details and PCB layout recommendations).
:H &
:H &R R QQHFW
QQHFW
AD26, AC24,
AE24, AD24,
AE26, AD25,
AC25, AC26,
AB24, AB25,
AB26, AB23,
AF23, AD23,
AF25, AE25,
AE23, AF24,
W25, W26,
W21, Y22,
see pin list
Y23, Y24,
W23, V23
Y25, Y26
AA25,
AA26,
AA24,
AA25,
AA23
AA26
Pin #
V25,
U25,
V24,
U22,
V25,
U24,
U25,
U26
V24
U26
O / I
I/O
IO
IO
O
O
O
O
O
DRAM Interface
Signal Description
Memory Data. These signals are connected to the DRAM data bus.
Note: MD0 is internally pulled up for use in EDO memory type
detection.
Memory Address. DRAM address lines. These pins are also used for
power-up strapping options (sampled on the rising edge of RESET#):
All pins have internal pull-downs for default low (0).
Strap 1 using 4.7K TO VCC3.
SDRAM Clock Enable. Clock enables 5-0 may be connected to the
DRAM modules in any order. Each DRAM module requires 2 clock
enables.
Note: These pins are powered by VSUS
Multifunction Pins
1. FPG/EDO DRAM: Row Address Strobe of each bank.
2. Synchronous DRAM: Chip select of each bank.
Note: These pins are powered by VSUS.
Multifunction Pins
1. FPG/EDO DRAM: Column Address Strobe of each byte lane.
2. Synchronous DRAM: Data mask of each byte lane.
Note: These pins are powered by VSUS.
Row Address Command Indicator.
Synchronous DRAM DIMM slots (these are copies of the same logical
signal). “A” controls banks 0-1 (module 0), “B” controls banks 2-3
(module 1), and “C” controls banks 4-5 (module 2).
Column Address Command Indicator. For support of up to three
Synchronous DRAM DIMM slots (these are copies of the same logical
signal). “A” controls banks 0-1 (module 0), “B” controls banks 2-3
(module 1), and “C” controls banks 4-5 (module 2).
Write Enable Command Indicator.
Synchronous DRAM DIMM slots (these are copies of the same logical
signal).
memory. “A” controls banks 0-1 (module 0), “B” controls banks 2-3
(module 1), and “C” controls banks 4-5 (module 2). Note: These pins
are powered by VSUS.
MA14,12 Rx68[1-0] CPU FSB Freq (0=66, 1=100, 2=auto, 3=133)
MA13
MA11
MA10-9
MA8, 6
MA7
MA5
MA4-2
MA1-0
-16-
Multifunction pins, used as MWE# pins for FPG/EDO
Rx52[7]
GTL I/O Buffer Pullup (0=Disable, 1=Enable)
In-order Queue Depth (0=1-level, 1=4-level)
North Bridge Clock Delay (0-3 Clocks)
Graphics Clock Select (0=Normal, 1-3=Test)
Graphics Test Mode (0=Normal, 1=Test)
LCD Output (0=Off, 1=On)
Panel Type (0-3=TFT, 4-7=DSTN)
Graphics Clock Delay (0-3 Clocks)
VT8601 Apollo ProMedia
For support of up to three
For support of up to three
Pinouts