VT8601 Via, VT8601 Datasheet - Page 50

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

PCI Bus Control
These registers are normally programmed once at system
initialization time.
Device 0 Offset 70 - PCI Buffer Control ......................... RW
Revision 1.3 September 8, 1999
7
6
5
4
3
2
1
0
7HFKQRORJLHV ,QF
CPU to PCI Post-Write
PCI Master to DRAM Post-Write
Reserved
PCI Master to DRAM Prefetch Disable
CPU-to-PCI Buffer Available Cycle Reduction
PCI Master Read Caching
Delay Transaction
Slave Device Stopped Idle Cycle Reduction
:H &
:H &R R QQHFW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Enable.....................................................default
Disable
Normal operation ...................................default
Reduce 1 cycle when the CPU-to-PCI buffer
becomes available after being full (PCI and
AGP buses)
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Normal Operation...................................default
Reduce 1 PCI idle cycle when stopped by a
slave device (PCI and AGP buses)
-44-
Device 0 Offset 71 - CPU to PCI Flow Control 1 ........... RW
bit-7 bit-3 Operation
7
6
5
4
3
2
1
0
0
0
1
Dynamic Burst
Byte Merge
Reserved (do not program) ........................default = 0
PCI I/O Cycle Post Write
PCI Burst
PCI Fast Back-to-Back Write
Quick Frame Generation
1 Wait State PCI Cycles
0
1
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disable................................................... default
Enable (see note under bit-3 below)
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable (bit7=1 will override this option)
Every write goes into the write buffer and no
PCI burst operations occur.
If the write transaction is a burst transaction,
the information goes into the write buffer and
burst transfers are later performed on the PCI
bus. If the transaction is not a burst, PCI write
occurs immediately (after a write buffer flush).
Every write transaction goes to the write
buffer; burstable transactions will then burst
on the PCI bus and non-burstable won’t. This
is the normal setting.
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
Device 0 Bus 0 Host Bridge Registers
VT8601 Apollo ProMedia