VT8601 Via, VT8601 Datasheet - Page 58

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge
All registers are located in PCI configuration space. They
should be programmed using PCI configuration mechanism 1
through CF8 / CFC with bus number and function number
equal to zero and device number equal to one.
Device 1 Offset 1-0 - Vendor ID ........................................ RO
Device 1 Offset 3-2 - Device ID .......................................... RO
Device 1 Offset 5-4 - Command ........................................ RW
Revision 1.3 September 8, 1999
15-10 Reserved
15-0 ID Code (reads 1106h to identify VIA Technologies)
15-0 ID Code (reads 8601h to identify the VT8601 PCI-
9
8
7
6
5
4
3
2
1
0
7HFKQRORJLHV ,QF
to-PCI Bridge device)
Fast Back-to-Back Cycle Enable ........................ RO
SERR# Enable...................................................... RO
(SERR# is used to report parity errors if bit-6 is set).
Address / Data Stepping ...................................... RO
Parity Error Response........................................RW
VGA Palette Snoop .............................................. RO
Memory Write and Invalidate Command.......... RO
Special Cycle Monitoring .................................... RO
Bus Master .........................................................RW
Memory Space.....................................................RW
I/O Space
:H &
:H &R R QQHFW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Fast back-to-back transactions only allowed to
the same agent ........................................default
Fast back-to-back transactions allowed to
different agents
SERR# driver disabled ...........................default
SERR# driver enabled
Device never does stepping....................default
Device always does stepping
Ignore parity errors & continue ..............default
Take normal action on detected parity errors
Treat palette accesses normally ..............default
Don’t respond to palette writes on PCI bus
(10-bit decode of I/O addresses 3C6-3C9 hex)
Bus masters must use Mem Write ..........default
Bus masters may generate Mem Write & Inval
Does not monitor special cycles .............default
Monitors special cycles
Never behaves as a bus master
Enable to operate as a bus master on the
primary interface on behalf of a master on the
secondary interface ................................default
Does not respond to memory space
Enable memory space access .................default
Does not respond to I/O space
Enable I/O space access ........................default
.........................................................RW
........................................ always reads 0
-52-
Device 1 Offset 7-6 - Status (Primary Bus) .................. RWC
Device 1 Offset 8 - Revision ID ......................................... RO
Device 1 Offset 9 - Programming Interface ..................... RO
This register is defined in different ways for each Base/Sub-
Class Code value and is undefined for this type of device.
Device 1 Offset A - Sub Class Code .................................. RO
Device 1 Offset B - Base Class Code ................................. RO
Device 1 Offset D - Latency Timer ................................... RO
Device 1 Offset E - Header Type ...................................... RO
Device 1 Offset F - Built In Self Test (BIST) ................... RO
10-9 DEVSEL# Timing
3-0
7-0
7-0
7-0
7-0
7-0
7-0
5-4
3-0
15
14
13
12
11
8
7
6
5
4
7
6
Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge
Detected Parity Error ........................ always reads 0
Signaled System Error (SERR#) ....... always reads 0
Signaled Master Abort
Received Target Abort
Signaled Target Abort........................ always reads 0
Data Parity Error Detected ...............always reads 0
Fast Back-to-Back Capable ...............always reads 0
User Definable Features.....................always reads 0
66MHz Capable..................................always reads 1
Supports New Capability list.............always reads 0
Reserved
VT8601 Chip Revision Code (00=First Silicon)
Interface Identifier ...........................always reads 00
Sub Class Code .reads 04 to indicate PCI-PCI Bridge
Base Class Code.. reads 06 to indicate Bridge Device
Reserved
Header Type Code.......... reads 01: PCI-PCI Bridge
BIST Supported...... reads 0: no supported functions
Start Test
Reserved
Response Code ..........0 = test completed successfully
00 Fast
01 Medium....................................always reads 01
10 Slow
11 Reserved
0
1
0
1
No abort received .................................. default
Transaction aborted by the master with
Master-Abort (except Special Cycles) ..............
No abort received .................................. default
Transaction aborted by the target with Target-
Abort ....................................... write 1 to clear
....................................... write 1 to clear
........................................always reads 0
........................................always reads 0
.......... write 1 to start but writes ignored
........................................always reads 0
VT8601 Apollo ProMedia