VT8601 Via, VT8601 Datasheet - Page 40

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Register Descriptions
Device 0 Bus 0 Header Registers - Host Bridge
All registers are located in PCI configuration space. They
should be programmed using PCI configuration mechanism 1
through CF8 / CFC with bus number, function number, and
device number equal to zero.
Device 0 Offset 1-0 - Vendor ID ........................................ RO
Device 0 Offset 3-2 - Device ID .......................................... RO
Device 0 Offset 5-4 - Command ........................................ RW
Revision 1.3 September 8, 1999
15-10 Reserved
15-0 ID Code (reads 1106h to identify VIA Technologies)
15-0 ID Code (reads 0601h to identify the VT8601)
9
8
7
6
5
4
3
2
1
0
7HFKQRORJLHV ,QF
Fast Back-to-Back Cycle Enable ........................ RO
SERR# Enable...................................................... RO
(SERR# is used to report parity errors if bit-6 is set).
Address / Data Stepping ...................................... RO
Parity Error Response........................................RW
VGA Palette Snoop .............................................. RO
Memory Write and Invalidate Command.......... RO
Special Cycle Monitoring .................................... RO
Bus Master .......................................................... RO
Memory Space...................................................... RO
I/O Space
:H &
:H &R R QQHFW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Fast back-to-back transactions only allowed to
the same agent ........................................default
Fast back-to-back transactions allowed to
different agents
SERR# driver disabled ...........................default
SERR# driver enabled
Device never does stepping....................default
Device always does stepping
Ignore parity errors & continue ..............default
Take normal action on detected parity errors
Treat palette accesses normally ..............default
Don’t respond to palette accesses on PCI bus
Bus masters must use Mem Write ..........default
Bus masters may generate Mem Write & Inval
Does not monitor special cycles .............default
Monitors special cycles
Never behaves as a bus master
Can behave as a bus master ....................default
Does not respond to memory space
Responds to memory space ....................default
Does not respond to I/O space ...............default
Responds to I/O space
.......................................................... RO
........................................ always reads 0
-34-
Device 0 Offset 7-6 - Status ........................................... RWC
Device 0 Offset 8 - Revision ID ......................................... RO
Device 0 Offset 9 - Programming Interface ..................... RO
Device 0 Offset A - Sub Class Code .................................. RO
Device 0 Offset B - Base Class Code ................................. RO
Device 0 Offset D - Latency Timer .................................. RW
Specifies the latency timer value in PCI bus clocks.
10-9 DEVSEL# Timing
3-0
7-0
7-0
7-0
7-0
7-3
2-0
15
14
13
12
11
8
7
6
5
4
Detected Parity Error
Signaled System Error (SERR# Asserted)
Signaled Master Abort
Received Target Abort
Signaled Target Abort........................ always reads 0
Data Parity Error Detected
Fast Back-to-Back Capable ............... always reads 1
Reserved
66MHz Capable..................................always reads 0
Supports New Capability list............. always reads 1
Reserved
VT8601 Chip Revision Code
Interface Identifier ........................... always reads 00
Sub Class Code .......reads 00 to indicate Host Bridge
Base Class Code.. reads 06 to indicate Bridge Device
Guaranteed Time Slice for CPU................default=0
Reserved (fixed granularity of 8 clks) .. always read 0
Bits 2-1 are writeable but read 0 for PCI specification
compatibility. The programmed value may be read
back in Offset 75 bits 5-4 (PCI Arbitration 1).
00 Fast
01 Medium....................................always reads 01
10 Slow
11 Reserved
0
1
0
1
0
1
0
0
1
Device 0 Bus 0 Header Registers - Host Bridge
No parity error detected ......................... default
Error detected in either address or data phase.
This bit is set even if error response is disabled
(command register bit-6). ......write one to clear
No abort received .................................. default
Transaction aborted by the master ...................
No abort received .................................. default
Transaction aborted by the target......................
Target Abort never signaled
No data parity error detected ................. default
Error detected in data phase. Set only if error
response enabled via command bit-6 = 1 and
VT8601 was initiator of the operation in which
the error occurred. .................write one to clear
........................................ always reads 0
....................................write one to clear
....................................... write 1 to clear
........................................ always reads 0
........................................always reads 0
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