VT8601 Via, VT8601 Datasheet - Page 21

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Signal Name
HA[31:3]#
HD[63:0]#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
BREQ0#
HREQ[4:0]#
HTRDY#
RS[2:0]#
CPURST#
CPURSTD#
Note: Clocking of the CPU and cache interfaces is performed with HCLK; see the clock pin group at the end of the pin
Note: All signals above require 4.7K pullups to VCC3 except EADS#, HITM#, AHOLD, HA, and HD.
Note: All signals above connect directly to the host CPU except HA and HD which connect directly to the L2 cache SRAMs and
Revision 1.3 September 8, 1999
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descriptions section for descriptions of the clock input pins.
connect to the host CPU through 22 ohm series resistors (see the “Apollo ProMedia Design Guide” for more information).
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see pin list
see pin list
H25, K23,
E25, F25,
F24, F23,
Pin #
D26
E26
H26
G24
G26
G23
E24
G25
H23
A19
E22
F26
J24
J23
J25
I/O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
O
O
I
I
Signal Description
Host Address Bus. Connect to the address bus of the host CPU. These pins are inputs
during CPU cycles, but are driven by the VT8601 during cache snooping operations.
Host CPU Data. These signals are connected to the CPU data bus.
Address Strobe. The CPU asserts ADS# in T1 of the CPU bus cycle.
Block Next Request. Used to block the current request bus owner from issuing new
requests. This signal is used to dynamically control the processor bus pipeline depth.
Priority Agent Bus Request. The owner of this signal will always be the next bus owner.
This signal has priority over symmetric bus requests and causes the current symmetric
owner to stop issuing new transactions unless the HLOCK# signal is asserted.
VT82C693 drives this signal to gain control of the processor bus.
Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring
more than one cycle.
Defer. The VT8601 uses a dynamic deferring policy to optimize system performance. The
VT8601 also uses the DEFER# signal to indicate a processor retry response.
Data Ready. Asserted for each cycle that data is transferred.
Hit. Indicates that a cacheing agent holds an unmodified version of the requested line.
Also driven in conjunction with HITM# by the target to extend the snoop window.
Hit Modified. Asserted by the CPU to indicate that the address presented with the last
assertion of EADS# is modified in the L1 cache and needs to be written back.
Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until the
negation of HLOCK# must be atomic.
Bus Request 0. Bus request output to CPU.
Request Command. Asserted during both clocks of the request phase. In the first clock,
the signals define the transaction type to a level of detail that is sufficient to begin a snoop
request. In the second clock, the signals carry additional information to define the complete
transaction type.
Host Target Ready. Indicates that the target of the processor transaction is able to enter
the data transfer phase.
Response Signals. Indicates the type of response per the table below:
CPU Reset. Reset output to CPU
CPU Reset Delayed. CPU Reset output delayed by 2T.
RS[2:0]#
000
001
010
011
100
101
110
111
Table 1. VT8601 Pin Descriptions
P
IN
Response type
Idle State
Retry Response
Defer Response
Reserved
Hard Failure
Normal Without Data
Implicit Writeback
Normal With Data
D
CPU Interface
ESCRIPTIONS
-15-
VT8601 Apollo ProMedia
Pinouts
The