VT8601 Via, VT8601 Datasheet - Page 56

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

AGP Control
Device 0 Offset A3-A0 - AGP Capability Identifier ........ RO
Device 0 Offset A7-A4 - AGP Status ................................. RO
Device 0 Offset AB-A8 - AGP Command ........................ RW
Revision 1.3 September 8, 1999
31-24 Reserved
23-20 Major Specification Revision ..... always reads 0001
19-16 Minor Specification Revision ..... always reads 0000
31-24 Maximum AGP Requests ................ always reads 07
23-10 Reserved
31-24 Request Depth (reserved for target)...always reads 0s
23-10 Reserved
15-8 Pointer to Next Item........ always reads 00 (last item)
7-0
8-2
7-2
9
1
0
9
8
1
0
7HFKQRORJLHV ,QF
Major revision # of AGP spec device conforms to
Minor revision # of AGP spec device conforms to
AGP ID
Max # of AGP requests the device can manage (8)
Supports SideBand Addressing ........ always reads 1
Reserved
2X Rate Supported
Value returned can be programmed by writing to
RxAC[3]
1X Rate Supported............................. always reads 1
SideBand Addressing Enable
AGP Enable
Reserved
2X Mode Enable
1X Mode Enable
:H &
:H &R R QQHFW
0
1
0
1
0
1
0
1
QQHFW
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
........................................ always reads 1
...................................... always reads 00
.. (always reads 02 to indicate it is AGP)
.......................................always reads 0s
.......................................always reads 0s
.......................................always reads 0s
.......................................always reads 0s
-50-
Device 0 Offset AC - AGP Control .................................. RW
Device 0 Offset AD – AGP Latency Register.................. RW
7-4
3-0
7
6
5
4
3
2
1
0
Reserved
AGP Read Synchronization
AGP Read Snoop CMFIFO
AGP Master Request has Higher Priority if AGP
Controller is Parking at AGP Master
2X Rate Supported (read also at RxA4[1])
LPR In-Order Access (Force Fence)
AGP Arbitration Parking
2T AGP to DRAM Request Generation
Reserved
AGP Latency Timer(units of 16 GCLKs)
0000 Free Run ................................................ default
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disable................................................... default
Enable (the CPU to AGP cycle will be delayed
if the CMFIFO contains a GART access)
Disable................................................... default
Enable (AGP read address will snoop the
CMFIFO; if hit, AGP read will be started after
the write is retired)
Disable................................................... default
Enable
Not supported ........................................ default
Supported
Fence/Flush functions not guaranteed. AGP
read requests (low/normal priority and high
priority) may be executed before previously
issued write requests. ............................. default
Force all requests to be executed in order
(automatically enables Fence/Flush functions).
Low (i.e., normal) priority AGP read requests
will never be executed before previously
issued writes. High priority AGP read requests
may still be executed prior to previously issued
write requests as required.
Disable................................................... default
Enable (GGNT# remains asserted until either
GREQ# de-asserts or data phase ready)
Disable................................................... default
Enable
...................................... always reads 0s
...................................... always reads 0s
Device 0 Bus 0 Host Bridge Registers
VT8601 Apollo ProMedia