MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 145

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

10.15 Equivalent Circuit for ADC Inputs
Figure 10-17
at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample
and hold circuit moves to (V
the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (V
switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that
there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter
into the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V
Freescale Semiconductor
5. LSB = Least Significant Bit = 0.806mV
6. Pin groups are detailed following
7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the
1.
2.
3.
4.
ADC.
Analog Input
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
Equivalent resistance for the channel select mux; 100 ohms
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
REF
illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
, and the ADC clock frequency.
1
Figure 10-17 Equivalent Circuit for A/D Loading
REFHx
2
Table
- V
10-1.
56F8035/56F8025 Data Sheet, Rev. 6
REFLx
125
(V
) / 2, while the other charges to the analog input voltage. When
REFHx
ESD Resistor
3
- V
REFL x
) / 2
8pF noise damping capacitor
S1
S2
REFHx
4
S3
- V
C2
C1
REFLx
Equivalent Circuit for ADC Inputs
S/H
) / 2. The switches
C1 = C2 = 1pF
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