MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 9

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

Award-Winning Development Environment
security systems, switched-mode power supply, power management, and medical monitoring
applications.
The 56800E core is based on a dual Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient, compact
DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F8035/56F8025 supports program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. The 56F8035/56F8025 also offers up to 35
General-Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F8035 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified
Data/Program RAM. The 56F8025 Digital Signal Controller includes 32KB of Program Flash and 4KB of
Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.
Program Flash page erase size is 512 Bytes (256 Words).
A full set of programmable peripherals — PWM, ADCs, QSCI, QSPI, I2C, PITs, Quad Timers, DACs,
and analog comparators — supports various applications. Each peripheral can be independently shut down
to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).
1.3 Award-Winning Development Environment
TM
Processor Expert
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and
development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs
create a complete, scalable tools solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8035/56F8025’s architecture is shown in
Figures
1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7.
Figure 1-1
illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and
the internal connections between each unit of the 56800E core.
Figure 1-2
shows the peripherals and
control blocks connected to the IPBus Bridge.
Figures
1-3, 1-4, 1-5, 1-6, and
1-7
detail how the device’s
I/O pins are muxed. The figures do not show the on-board regulator and power and ground signals. Please
see
Part 2, Signal/Connection
Descriptions, for information about which signals are multiplexed with
those of other peripherals.
1.4.1
PWM, TMR and ADC Connections
Figure 1-6
shows the over-limit and under-limit connections from the ADC to the PWM and the
connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar
manner as the PWM generator. See the 56F802x and 56F803x Peripheral Reference Manual for
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
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