MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 22

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

2.2 56F8035/56F8025 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
22
Return to
(GPIOA7)
RESET
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal
Name
V
V
V
V
V
V
V
V
V
DDA
SSA
CAP
CAP
DD
DD
SS
SS
SS
Table 2-2
Pin No.
LQFP
29
35
17
28
36
11
12
18
34
21
Input/Open
Supply
Supply
Supply
Supply
Supply
Output
Type
Drain
Input
State During
enabled
internal
Supply
Supply
Supply
Supply
Supply
pull-up
Reset
Input,
56F8035/56F8025 Data Sheet, Rev. 6
I/O Power — This pin supplies 3.3V power to the chip I/O interface.
V
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
V
order to bypass the core voltage regulator, required for proper chip
operation. See
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
SS
CAP
— These pins provide ground for chip logic and I/O drivers.
— Connect this pin to a 2.2 F or greater bypass capacitor in
Section
10.2.1.
Signal Description
Freescale Semiconductor