MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 45

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

Freescale Semiconductor
TMRA3_CSCTRL
TMRA3_FILT
ADC_CTRL1
ADC_CTRL2
ADC_ZXCTRL
ADC_CLIST 1
ADC_CLIST 2
ADC_CLIST 3
ADC_CLIST 4
ADC_SDIS
ADC_STAT
ADC_RDY
ADC_LIMSTAT
ADC_ZXSTAT
ADC_RSLT0
ADC_RSLT1
ADC_RSLT2
ADC_RSLT3
ADC_RSLT4
ADC_RSLT5
ADC_RSLT6
ADC_RSLT7
ADC_RSLT8
ADC_RSLT9
ADC_RSLT10
ADC_RSLT11
ADC_RSLT12
ADC_RSLT13
ADC_RSLT14
ADC_RSLT15
ADC_LOLIM0
Register Acronym
Register Acronym
Table 4-10 Analog-to-Digital Converter Registers Address Map
Table 4-9 Quad Timer A Registers Address Map (Continued)
Address Offset
Address Offset
56F8035/56F8025 Data Sheet, Rev. 6
(TMRA_BASE = $00 F000)
$3A
$3B
$1A
$1B
$1C
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
(ADC_BASE = $00 F080)
$C
$D
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$E
$F
Comparator Status and Control Register
Input Filter Register
Reserved
Control Register 1
Control Register 2
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Channel List Register 3
Channel List Register 4
Sample Disable Register
Status Register
Conversion Ready Register
Limit Status Register
Zero Crossing Status Register
Result Register 0
Result Register 1
Result Register 2
Result Register 3
Result Register 4
Result Register 5
Result Register 6
Result Register 7
Result Register 8
Result Register 9
Result Register 10
Result Register 11
Result Register 12
Result Register 13
Result Register 14
Result Register 15
Low Limit Register 0
Register Description
Register Description
Peripheral Memory-Mapped Registers
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