MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 94

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.12.8
6.3.12.9
6.3.13
In I/O short address mode, the instruction specifies only 6 LSBs of the effective address; the upper 18 bits
are “hard coded” to a specific area of memory. This scheme allows efficient access to a 64-location area
in peripheral space with single word instruction. Short address location registers specify the upper 18 bits
of I/O address, which are “hard coded”. These registers allow access to peripherals using I/O short address
mode, regardless of the physical location of the peripheral, as shown in
With this register set, software can set the SIM_IOSAHI and SIM_IOSALO registers to point to its
peripheral registers and then use the I/O short addressing mode to access them.
Note:
Note:
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0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
I/O Short Address Location Register High (SIM_IOSAHI)
The default value of this register set points to the EOnCE registers.
The pipeline delay between setting this register set and using short I/O addressing with the new value
is five instruction cycles.
Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)—Bit 1
Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)—Bit 0
2 bits from SIM_IOSAHI Register
Full 24-Bit for Short I/O Address
16 Bits from SIM_IOSALO Register
Figure 6-14 I/O Short Address Determination
6 Bits from I/O Short Address Mode Instruction
56F8035/56F8025 Data Sheet, Rev. 6
“
Hard Coded” Address Portion
Figure
Instruction Portion
6-14.
Freescale Semiconductor