MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 56

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), to signals
the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to
service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
For further information, see
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt
sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next,
all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value
of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority
and number 63 is the lowest.
5.3.1
Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base
Address (VBA) and the vector number to determine the vector address, generating an offset into the vector
table for each interrupt.
5.3.2
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The 56800E core controls the masking of interrupt priority levels it will accept by setting the I0
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Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Ability to drive initial address on the address bus after reset
FM_IFROPT_1
FM_TSTSIG
Register Acronym
Normal Interrupt Handling
Interrupt Nesting
Table 4-31 Flash Module Registers Address Map
Table
(FM_BASE = $00 F400) (Continued)
Address Offset
4-2, Interrupt Vector Table Contents.
56F8035/56F8025 Data Sheet, Rev. 6
$1B
$1C
$1D
Information Option Register 1
Reserved
Test Array Signature Register
Register Description
Freescale Semiconductor