MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 84

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.2
This read-only register is updated upon any system reset and indicates the cause of the most recent reset.
It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External
Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On
Reset and subsequently is synchronously updated based on the precedence level of reset inputs. Only the
most recent reset source will be indicated if multiple resets occur. If multiple reset sources assert
simultaneously, the highest-precedence source will be indicated. The precedence from highest to lowest is
Power-On Reset, External Reset, COP Loss of Reference Reset, COP Time-Out Reset, and Software
Reset. Power-On Reset is always set during a Power-On Reset; however, Power-On Reset will be cleared
and External Reset will be set if the external reset pin is asserted or remains asserted after the Power-On
Reset has deasserted.
6.3.2.1
This bit field is reserved. Each bit must be set to 0.
6.3.2.2
When set, this bit indicates that the previous system reset occurred as a result of a software reset (written
1 to SWRST bit in the SIM_CTRL register).
6.3.2.3
When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly
(COP) module signaling a COP time-out reset. If COP_TOR is set as code starts executing, the COP reset
vector in the vector table will be used. Otherwise, the normal reset vector is used.
6.3.2.4
When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly
(COP) module signaling a loss of COP reference clock reset. If COP_LOR is set as code starts executing,
the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.
6.3.2.5
When set, this bit indicates that the previous system reset was caused by an external reset.
6.3.2.6
This bit is set during a Power-On Reset.
84
Base + $1
RESET
Read
Write
SIM Reset Status Register (SIM_RSTAT)
Reserved—Bits 15–7
Software Reset (SWR)—Bit 6
COP Time-Out Reset (COP_TOR)—Bit 5
COP Loss of Reference Reset (COP_LOR)—Bit 4
External Reset (EXTR)—Bit 3
Power-On Reset (POR)—Bit 2
15
0
0
Figure 6-3 SIM Reset Status Register (SIM_RSTAT)
14
0
0
13
0
0
12
0
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
SWR
6
0
COP_
TOR
5
0
COP_
LOR
4
0
EXTR
3
0
Freescale Semiconductor
POR
2
1
1
0
0
0
0
0