MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 89

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.9.3
6.3.9.4
6.3.9.5
This bit field is reserved. It must be set to 0.
6.3.9.6
6.3.9.7
This bit field is reserved. Each bit must be set to 0.
6.3.9.8
6.3.9.9
This bit field is reserved. It must be set to 0.
6.3.9.10
6.3.9.11
This bit field is reserved. It must be set to 0.
6.3.9.12
6.3.9.13
This bit field is reserved. It must be set to 0.
6.3.9.14
Freescale Semiconductor
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0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled)
1 = The clock is enabled to the DAC1 module
0 = The clock is not provided to the DAC0 module (the DAC0 module is disabled)
1 = The clock is enabled to the DAC0 module
0 = The clock is not provided to the ADC module (the ADC module is disabled)
1 = The clock is enabled to the ADC module
0 = The clock is not provided to the I
1 = The clock is enabled to the I
0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled)
1 = The clock is enabled to the QSCI0 module
0 = The clock is not provided to the QSPI0 module (the QSPI0 module is disabled)
1 = The clock is enabled to the QSPI0 module
0 = The clock is not provided to the PWM module (the PWM module is disabled)
Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13
Digital-to-Analog Clock Enable 0 (DAC0)—Bit 12
Reserved—Bit 11
Analog-to-Digital Converter Clock Enable (ADC)—Bit 10
Reserved—Bits 9–7
Inter-Integrated Circuit IPBus Clock Enable (I2C)—Bit 6
Reserved—Bit 5
QSCI 0 Clock Enable (QSCI0)—Bit 4
Reserved—Bit 3
QSPI 0 Clock Enable (QSPI0)—Bit 2
Reserved—Bit 1
PWM Clock Enable (PWM)—Bit 0
56F8035/56F8025 Data Sheet, Rev. 6
2
C module
2
C module (the I
2
C module is disabled)
Register Descriptions
89