MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 90

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.10
See
6.3.10.1
This bit field is reserved. It must be set to 0.
6.3.10.2
6.3.10.3
6.3.10.4
6.3.10.5
This bit field is reserved. Each bit must be set to 0.
6.3.10.6
6.3.10.7
6.3.10.8
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Section 6.3.9
Base + $D
RESET
Write
Read
1 = The clock is enabled to the PWM module
0 = The clock is not provided to the PIT2 module (the PIT2 module is disabled)
1 = The clock is enabled to the PIT2 module
0 = The clock is not provided to the PIT1 module (the PIT1 module is disabled)
1 = The clock is enabled to the PIT1 module
0 = The clock is not provided to the PIT0 module (the PIT0 module is disabled)
1 = The clock is enabled to the PIT0 module
0 = The clock is not provided to the Timer A3 module (the Timer A3 module is disabled)
1 = The clock is enabled to the Timer A3 module
0 = The clock is not provided to the Timer A2 module (the Timer A2 module is disabled)
1 = The clock is enabled to the Timer A2 module
0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled)
1 = The clock is enabled to the Timer A1 module
Peripheral Clock Enable Register 1 (SIM_PCE1)
Reserved—Bit 15
Programmable Interval Timer 2 Clock Enable (PIT2)—Bit 14
Programmable Interval Timer 1 Clock Enable (PIT1)—Bit 13
Programmable Interval Timer 0 Clock Enable (PIT0)—Bit 12
Reserved—Bits 11–4
Quad Timer A, Channel 3 Clock Enable (TA3)—Bit 3
Quad Timer A, Channel 2 Clock Enable (TA2)—Bit 2
Quad Timer A, Channel 1 Clock Enable (TA1)—Bit 1
15
Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1)
0
0
for general information about Peripheral Clock Enable registers.
PIT2
14
0
PIT1
13
0
PIT0
12
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
0
4
0
0
TA3
3
0
Freescale Semiconductor
TA2
2
0
TA1
1
0
TA0
0
0