MC56F8035VLDR Freescale Semiconductor, MC56F8035VLDR Datasheet - Page 5

• Manufacturer Part Number: MC56F8035VLDR
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLDR

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6
Part 2 Signal/Connection Descriptions . . . 18
Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 33
Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 36
Part 5 Interrupt Controller (ITCN) . . . . . . . . 56
Part 6 System Integration Module (SIM) . . . 79
Part 7 Security Features. . . . . . . . . . . . . . . 112
Freescale Semiconductor
1.1
1.2
1.3
1.4
1.5
1.6
2.1
2.2
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.1
4.2
4.3
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7.1
7.2
56F8035/56F8025 Features . . . . . . . . . . . 6
56F8035/56F8025 Description . . . . . . . . . 8
Award-Winning Development
Architecture Block Diagram . . . . . . . . . . . 9
Product Documentation . . . . . . . . . . . . . 17
Data Sheet Conventions . . . . . . . . . . . . . 17
Introduction . . . . . . . . . . . . . . . . . . . . . . . 18
56F8035/56F8025 Signal Pins . . . . . . . . 22
Overview . . . . . . . . . . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating Modes . . . . . . . . . . . . . . . . . . 33
Internal Clock Source . . . . . . . . . . . . . . . 34
Crystal Oscillator. . . . . . . . . . . . . . . . . . . 34
Ceramic Resonator . . . . . . . . . . . . . . . . . 35
External Clock Input - Crystal Oscillator
Alternate External Clock Input . . . . . . . . 36
Introduction . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Vector Table . . . . . . . . . . . . . . . 37
Program Map . . . . . . . . . . . . . . . . . . . . . 39
Data Map . . . . . . . . . . . . . . . . . . . . . . . . 39
EOnCE Memory Map . . . . . . . . . . . . . . . 41
Peripheral Memory-Mapped Registers . . 42
Introduction . . . . . . . . . . . . . . . . . . . . . . . 56
Features . . . . . . . . . . . . . . . . . . . . . . . . . 56
Functional Description . . . . . . . . . . . . . . 56
Block Diagram. . . . . . . . . . . . . . . . . . . . . 59
Operating Modes . . . . . . . . . . . . . . . . . . 59
Register Descriptions . . . . . . . . . . . . . . . 59
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Introduction . . . . . . . . . . . . . . . . . . . . . . . 79
Features . . . . . . . . . . . . . . . . . . . . . . . . . 80
Register Descriptions . . . . . . . . . . . . . . . 81
Clock Generation Overview . . . . . . . . . 106
Power-Saving Modes . . . . . . . . . . . . . . 108
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 109
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 112
Operation with Security Enabled. . . . . . 112
Flash Access Lock and Unlock
Environment . . . . . . . . . . . . . . . . . . . 9
Option. . . . . . . . . . . . . . . . . . . . . . . 35
Mechanisms . . . . . . . . . . . . . . . . . 113
56F8035/56F8025 Data Sheet Table of Contents
56F8035/56F8025 Data Sheet, Rev. 6
Part 8 General-Purpose Input/Output
Part 9 Joint Test Action Group (JTAG) . . .122
Part 10Specifications. . . . . . . . . . . . . . . . . .122
Part 11Packaging . . . . . . . . . . . . . . . . . . . . .149
Part 12Design Considerations . . . . . . . . . .155
Part 13Ordering Information . . . . . . . . . . . .157
Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .158
7.3
8.1
8.2
8.3
9.1
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
11.1
12.1
12.2
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . .114
Product Analysis. . . . . . . . . . . . . . . . . . 114
Introduction. . . . . . . . . . . . . . . . . . . . . . 114
Configuration . . . . . . . . . . . . . . . . . . . . 114
Reset Values . . . . . . . . . . . . . . . . . . . . 117
56F8035/56F8025 Information . . . . . . . 122
General Characteristics . . . . . . . . . . . . 122
DC Electrical Characteristics . . . . . . . . 126
AC Electrical Characteristics . . . . . . . . 129
Flash Memory Characteristics . . . . . . . 130
External Clock Operation Timing . . . . . 130
Phase Locked Loop Timing . . . . . . . . . 131
Relaxation Oscillator Timing. . . . . . . . . 132
Reset, Stop, Wait, Mode Select, and
Serial Peripheral Interface (SPI)
Quad Timer Timing. . . . . . . . . . . . . . . . 138
Serial Communication Interface (SCI)
Inter-Integrated Circuit Interface (I2C)
JTAG Timing. . . . . . . . . . . . . . . . . . . . . 143
Analog-to-Digital Converter (ADC)
Equivalent Circuit for ADC Inputs . . . . . 145
Comparator (CMP) Parameters . . . . . . 146
Digital-to-Analog Converter (DAC)
Power Consumption . . . . . . . . . . . . . . . 148
56F8035/56F8025 Package and
Thermal Design Considerations . . . . . . 155
Electrical Design Considerations . . . . . 156
Interrupt Timing . . . . . . . . . . . . . . 133
Timing . . . . . . . . . . . . . . . . . . . . . 134
Timing . . . . . . . . . . . . . . . . . . . . . 140
Timing . . . . . . . . . . . . . . . . . . . . . 141
Parameters . . . . . . . . . . . . . . . . . 144
Parameters . . . . . . . . . . . . . . . . . 146
Pin-Out Information . . . . . . . . . . . 149
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