MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 105

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.22.1
This bit field is reserved. Each bit must be set to 0.
6.3.22.2
This field selects the alternate input source signal to feed DAC1 SYNC input.
6.3.22.3
This bit field is reserved. It must be set to 0.
6.3.22.4
This field selects the alternate input source signal to feed DAC0 SYNC input.
6.3.23
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Freescale Semiconductor
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Section 6.3.21
Base + $19
RESET
Read
Write
000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default)
001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input
010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input
011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input
100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input
101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input
11x = Reserved
000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default)
001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input
010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input
011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input
100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input
101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input
11x = Reserved
Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1)
Internal Peripheral Source Select Register 2 for Quad Timer A
(SIM_IPS2)
Reserved—Bits 15–7
Select Input Source for SYNC Input to DAC 1 (IPS1_DSYNC1)—Bits 6–4
Reserved—Bit 3
Select Peripheral Input Source for SYNC Input to DAC 0
(IPS1_DSYNC0)—Bits 2–0
15
0
0
for general information about Internal Peripheral Source Select registers.
14
0
0
13
0
0
12
0
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
IPS1_DSYNC1
5
0
4
0
3
0
0
2
0
IPS1_DSYNC0
Register Descriptions
1
0
0
0
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