MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 85

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.2.7
This bit field is reserved. Each bit must be set to 0.
6.3.3
These registers are general-purpose registers. They are reset only at power-on, so they can monitor
software execution flow.
6.3.3.1
This register is reset only by the Power-On Reset (POR). It is intended for use by a software developer to
contain data that will be unaffected by the other reset sources (external reset, software reset, and COP
reset).
6.3.4
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F2.
6.3.5
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$801D.
Freescale Semiconductor
Base + $2
Base + $6
Base + $7
RESET
RESET
RESET
Read
Write
Read
Write
Read
Write
SIM Software Control Registers (SIM_SWC0, SIM_SWC1,
SIM_SWC2, and SIM_SWC3)
Most Significant Half of JTAG ID (SIM_MSHID)
Least Significant Half of JTAG ID (SIM_LSHID)
Reserved—Bits 1–0
Software Control Register 0 - 3 (FIELD)—Bits 15–0
Figure 6-4 SIM Software Control Register 0 (SIM_SWC0 - 3)
15
15
15
0
0
0
1
1
Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)
Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)
14
14
14
0
0
0
0
0
13
13
13
0
0
0
0
0
12
12
12
0
0
0
0
0
56F8035/56F8025 Data Sheet, Rev. 6
11
11
11
0
0
0
0
0
10
10
10
0
0
0
0
0
Software Control Data 0 - 3
9
0
9
0
0
9
0
0
8
8
8
0
1
1
0
0
7
7
7
0
1
1
0
0
6
6
6
0
1
1
0
0
5
0
5
1
1
5
0
0
4
0
4
1
1
4
1
1
3
3
3
0
0
0
1
1
2
0
2
0
0
2
1
1
Register Descriptions
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
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