MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 27

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

Freescale Semiconductor
7
8
Return to
The TA2 signal is also brought out on the GPIOA4 and GPIOA8 pins.
The TA3 signal is also brought out on the GPIOA5 and GPIOA9 pins.
(PSRC0)
(PSRC1)
GPIOB2
(MISO0)
GPIOB3
(MOSI0)
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal
(TA2
(TA3
Name
7
8
)
)
Table 2-2
Pin No.
LQFP
23
22
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Input/
Type
Input
Input
State During
enabled
enabled
internal
internal
pull-up
pull-up
Reset
Input,
Input,
56F8035/56F8025 Data Sheet, Rev. 6
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
TA2 — Timer A, Channel 2
PSRC0 — External PWM signal source input for the complementary
PWM4/PWM5 pair.
After reset, the default state is GPIOB2. The peripheral functionality
is controlled via the SIM. See
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Master Out/Slave In— This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
TA3 — Timer A, Channel 3
PSRC1 — External PWM signal source input for the complementary
PWM2/PWM3 pair.
After reset, the default state is GPIOB3. The peripheral functionality
is controlled via the SIM. See
Signal Description
Section
Section
6.3.16.
6.3.16.
56F8035/56F8025 Signal Pins
27