MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 88

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.8.2
This bit selects the clock speed for the Quad Timer A module.
6.3.8.3
This bit selects the clock speed for the PWM module.
6.3.8.4
This bit selects the clock speed for the I
6.3.8.5
This bit field is reserved. Each bit must be set to 0.
6.3.9
The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings
feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use.
When a peripheral’s clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has
its clock disabled will have no effect. The corresponding peripheral should itself be disabled while its clock
is shut off. IPBus writes are not possible.
Setting the PCE bit does not guarantee that the peripheral’s clock is running. Enabled peripheral clocks
will still become disabled in Stop mode, unless the peripheral’s Stop Disable control in the SDn register
is set to 1.
6.3.9.1
6.3.9.2
88
Base + $C
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RESET
Read
Write
0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz
0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz
0 = I
1 = I
0 = The clock is not provided to the Comparator B module (the Comparator B module is disabled)
1 = The clock is enabled to the Comparator B module
0 = The clock is not provided to the Comparator A module (the Comparator A module is disabled)
1 = The clock is enabled to the Comparator A module
Peripheral Clock Enable Register 0 (SIM_PCE0)
2
2
Quad Timer A Clock Rate (TMRA_CR)—Bit 14
Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13
Inter-Integrated Circuit Run Clock Rate (I2C_CR)—Bit 12
C module run clock rate equals the system clock rate, to a maximum 32MHz (default)
C module run clock rate equals 3X system clock rate, to a maximum 96MHz
Reserved—Bits 11–0
Comparator B Clock Enable (CMPB)—Bit 15
Comparator A Clock Enable (CMPA)—Bit 14
CMPB
15
0
Figure 6-10 Peripheral Clock Enable Register 0 (SIM_PCE0)
CMPA
14
0
DAC1
13
0
DAC0
12
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
2
C run clock.
ADC
10
0
9
0
0
8
0
0
7
0
0
I2C
6
0
5
0
0
QSCI0
4
0
3
0
0
Freescale Semiconductor
QSPI0
2
0
1
0
0
PWM
0
0