MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 128

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

1. No Output Switching
STANDBY > STOP
POWERDOWN
10.2.1
The 56F8035/56F8025 has two on-chip regulators. One supplies the PLL and relaxation oscillator. It has
no external pins and therefore has no external characteristics which must be guaranteed (other than proper
operation of the device). The second regulator supplies approximately 2.5V to the 56F8035/56F8025’s
core logic. This regulator requires an external 4.4
128
All ports configured as inputs
All inputs Low
No DC Loads
Mode
1. When V
2. When V
3. Power-On Reset occurs whenever the internally regulated 2.5V digital supply drops below 1.8V. While
Low-Voltage Interrupt for 3.3V supply
Low-Voltage Interrupt for 2.5V supply
Low-Voltage Interrupt Recovery Hysteresis
Power-On Reset
power is ramping up, this signal remains active for as long as the internal 2.5V is below 2.15V or the 3.3V
1/O voltage is below 2.7V, no matter how long the ramp-up rate is. The internally regulated voltage is
typically 100mV less than V
Voltage Regulator Specifications
Table 10-6 Current Consumption per Power Supply Pin (Continued)
DD
DD
100kHz Device Clock
Relaxation Oscillator in Standby mode
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC/DAC/Comparator powered off
Voltage regulator in Standby mode
Device Clock is off
Relaxation Oscillator powered off
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC /DAC/Comparator powered off
Voltage Regulator in Standby mode
drops below V
drops below V
Table 10-7 Power-On Reset Low-Voltage Parameters
Characteristic
3
EI3.3
EI32.5
DD
Conditions
, an interrupt is generated.
, an interrupt is generated.
during ramp-up until 2.5V is reached, at which time it self-regulates.
56F8035/56F8025 Data Sheet, Rev. 6
1
2
Symbol
µ
V
F, or greater, capacitor for proper operation. Ceramic
V
POR
V
E12.5
EI3.3
EIH
2.58
Min
—
—
—
Typical @ 3.3V, 25°C
540 A
440 A
I
DD
1
2.15
Typ
2.7
1.8
50
I
0 A
0 A
DDA
Max
1.9
—
—
—
Freescale Semiconductor
Maximum@ 3.6V, 25°C
650 A
550 A
I
DD
Unit
mV
1
V
V
V
I
1 A
1 A
DDA