MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 96

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.15.1
This bit field is reserved. Each bit must be set to 0.
6.3.15.2
These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module.
6.3.15.3
These bits enable write protection of GPSn and IPSn registers in the SIM module and write protect all
GPIOx_PEREN, GPIOx_PPOUTM and GPIOx_DRIVE registers in GPIO modules.
Note:
6.3.16
Most I/O pins have an associated GPIO function. In addition to the GPIO function, I/O can be configured
to be one of several peripheral functions. The GPIOx_PEREN register within the GPIO module controls
the selection between peripheral or GPIO control of the I/O pins. The GPIO function is selected when the
GPIOx_PEREN bit for the I/O is 0. When the GPIOx_PEREN bit of the GPIO is 1, the fields in the GPSn
registers select which peripheral function has control of the I/O.
an I/O pin when an I/O has two peripheral functions. Similar muxing is required on peripheral function
inputs to receive input from the properly selected I/O pin.
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Base + $12
RESET
00 = Write protection off (default)
01 = Write protection on
10 = Write protection off and locked until chip reset
11 = Write protection on and locked until chip reset
00 = Write protection off (default)
01 = Write protection on
10 = Write protection off and locked until chip reset
11 = Write protection on and locked until chip reset
Write
Read
The PWM fields in the CLKOUT register are also write protected by GIPSP. They are reserved for
in-house test only.
SIM GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)
Reserved—Bits 15–4
Peripheral Clock Enable Protection (PCEP)—Bits 3–2
GPIO and Internal Peripheral Select Protection (GIPSP)—Bits 1–0
15
0
0
14
0
0
Figure 6-17 Protection Register (SIM_PROT)
13
0
0
12
0
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
Figure 6-18
6
0
0
5
0
0
4
0
0
illustrates the output path to
3
0
PCEP
Freescale Semiconductor
2
0
1
0
GIPSP
0
0