MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 4
MC56F8035VLD
Manufacturer Part Number
MC56F8035VLD
Description
Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
Manufacturer
Freescale Semiconductor
Datasheet
1.MC56F8035VLDR.pdf
(161 pages)
Specifications of MC56F8035VLD
Rohs
yes
Core
56800E
Data Bus Width
16 bit
Program Memory Size
64 KB
Data Ram Size
8 KB
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
35
Number Of Timers
3
Device Million Instructions Per Second
32 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Package / Case
LQFP-44
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC56F8035VLD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC56F8035VLDR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
56F8035/56F8025 General Description
4
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
• 56F8035 offers 64KB (32K x 16) Program Flash
• 56F8025 offers 32KB (16K x 16) Program Flash
• 56F8035 offers 8KB (4K x 16) Unified Data/Program
• 56F8025 offers 4KB (2K x 16) Unified Data/Program
• One 6-channel PWM module
• Two 4-channel 12-bit Analog-to-Digital Converters
• Two Internal 12-bit Digital-to-Analog Converters
C-efficient architecture
RAM
RAM
(ADCs)
(DACs)
11
4
4
Programmable
DAC
AD0
AD1
Interval
or GPIOC
Timer
or CMP
ADC
or GPIOB
or CMP
I
2
C
2
or TMRA or CMP
or GPIOA
PWM
or GPIOB
or TMRA
or PWM
or I
QSPI
4
2
C
Program Memory
16K x 16 Flash
32K x 16 Flash
Program RAM
Unified Data /
Memory
2K x 16
4K x 16
or GPIOB
or TMRA
or PWM
56F8035/56F8025 Block Diagram
or I
QSCI
2
IPBus Bridge (IPBB)
3
C
56F8035/56F8025 Data Sheet, Rev. 6
Program Controller
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
and Hardware
Watchdog
RESET or
Looping Unit
GPIOA
COP/
PAB
CDBR
CDBW
PDB
JTAG/EOnCE
Controller
Interrupt
Generation Unit
Port or
GPIOD
4
Address
• Two Analog Comparators
• Three Programmable Interval Timers (PITs)
• One Queued Serial Communication Interface (QSCI)
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
• Up to 35 GPIO lines
with LIN slave functionality
Interrupt (LVI) module
unobtrusive, real-time debugging
56800E Core
V
2
16-Bit
Integration
CAP
Three 16-bit Input Registers
System
Module
System Bus
16 x 16 + 36 -> 36-Bit MAC
Four 36-bit Accumulators
2
V
Control
DD
Digital Reg
Data ALU
P
O
R
3
V
Low-Voltage
SS
Supervisor
R/W Control
Relaxation Oscillator
Generator*
*Includes On-Chip
V
Clock
Analog Reg
DDA
V
Manipulation
SSA
O
C
S
Unit
Bit
Freescale Semiconductor
2
C) port
EXTAL or GPIOD
XTAL, CLKIN, or
GPIOD