MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 55

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

Freescale Semiconductor
I2C_RISTAT
I2C_RXFT
I2C_TXFT
I2C_CLRINT
I2C_CLRRXUND
I2C_CLRRXOVR
I2C_CLRTXOVR
I2C_CLRRDREQ
I2C_CLRTXABRT
I2C_CLRRXDONE
I2C_CLRACT
I2C_CLRSTPDET
I2C_CLRSTDET
I2C_CLRGC
I2C_ENBL
I2C_STAT
I2C_TXFLR
I2C_RXFLR
I2C_TXABRTSRC
FM_CLKDIV
FM_CNFG
FM_SECHI
FM_SECLO
FM_PROT
FM_USTAT
FM_CMD
FM_DATA
Register Acronym
Register Acronym
Table 4-30 I
Table 4-31 Flash Module Registers Address Map
Address Offset
$11 - $12
$15 - $17
$19 - $A
$5 - $9
2
56F8035/56F8025 Data Sheet, Rev. 6
$10
$13
$14
$18
C Registers Address Map (Continued)
$0
$1
$2
$3
$4
(I2C_BASE = $00 F280)
(FM_BASE = $00 F400)
Address Offset
$1A
$1C
$1E
$2A
$2C
$2E
$3A
$3C
$20
$22
$24
$26
$28
$30
$32
$34
$36
$38
$40
Clock Divider Register
Configuration Register
Reserved
Security High Half Register
Security Low Half Register
Reserved
Protection Register
Reserved
User Status Register
Command Register
Reserved
Data Buffer Register
Reserved
Raw Interrupt Status Register
Receive FIFO Threshold Register
Transmit FIFO Threshold Register
Clear Combined and Individual Interrupts Register
Clear RX_UNDER Interrupt Register
Clear RX_OVER Interrupt Register
Clear TX_OVER Interrupt Register
Clear RD_REQ Interrupt Register
Clear TX_ABRT Interrupt Register
Clear RX_DONE Interrupt Register
Clear Activity Interrupt Register
Clear STOP_DET Interrupt Register
Clear START_DET Interrupt Register
Clear GEN_CALL Interrupt Register
Enable Register
Status Register
Transmit FIFO Level Register
Receive FIFO Level Register
Transmit Abort Status Register
Register Description
Register Description
Peripheral Memory-Mapped Registers
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