MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 91

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

6.3.10.9
6.3.11
By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This
register will allow an individual peripheral to operate in Stop mode. Since asserting an interrupt causes the
system to return to Run mode, this feature is provided so that selected peripherals can be left operating in
Stop mode for the purpose of generating a wake-up interrupt.
For power-conscious applications, it is recommended that only a minimum set of peripherals be
configured to remain operational during Stop mode.
Peripherals should be put in a non-operating (disabled) configuration prior to entering Stop mode unless
their corresponding Stop Disable control is set to 1. Refer to the 56F802x and 56F803x Peripheral
Reference Manual for further details. Reads and writes cannot be made to a module that has its clock
disabled.
6.3.11.1
6.3.11.2
6.3.11.3
6.3.11.4
Freescale Semiconductor
Base + $E
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RESET
Read
Write
0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled)
1 = The clock is enabled to the Timer A0 module
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
Stop Disable Register 0 (SD0)
Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0
Comparator B Clock Stop Disable (CMPB_SD)—Bit 15
Comparator A Clock Stop Disable (CMPA_SD)—Bit 14
Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13
Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12
CMPB_
SD
15
0
CMPA_
SD
14
0
DAC1_
SD
13
Figure 6-12 Stop Disable Register 0 (SD0)
0
DAC0_
SD
12
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
ADC_
10
SD
0
9
0
0
8
0
0
7
0
0
I2C_
SD
6
0
5
0
0
QSCI0_
SD
4
0
3
0
0
QSPI0_
Register Descriptions
SD
2
0
1
0
0
PWM_
SD
0
0
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