LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 162

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 165. LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I
UM10398
User manual
Symbol
PIO0_0 to PIO0_11
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/SCK0
PIO0_8/MISO0/
CT16B0_MAT0
Fig 23. Pin configuration TSSOP20 package with I
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
SWDIO/PIO1_3/AD4/CT32B1_MAT2
17
18
19
20
5
6
1
R/PIO0_11/AD0/CT32B0_MAT3
PIO0_8/MISO0/CT16B0_MAT0
PIO0_9/MOSI0/CT16B0_MAT1
R/PIO1_0/AD1/CT32B1_CAP0
R/PIO1_1/AD2/CT32B1_MAT0
R/PIO1_2/AD3/CT32B1_MAT1
[2]
[3]
[3]
[4]
[4]
[3]
[3]
Start
logic
input
yes
yes
yes
yes
yes
yes
yes
PIO0_6/SCK0
PIO0_5/SDA
Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP,
Type Reset
I/O
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
state
[1]
I; PU
-
I; PU
-
-
I; PU
-
-
I; IA
-
I; IA
-
I; PU
-
I; PU
-
-
10
1
2
3
4
5
6
7
8
9
LPC1111FDH20/002
2
Description
Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends
on the function selected through the IOCONFIG register block.
RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0.
PIO0_0 — General purpose digital input/output pin with 10 ns glitch
filter.
PIO0_1 — General purpose digital input/output pin. A LOW level on
this pin during reset starts the ISP command handler.
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave Select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_4 — General purpose digital input/output pin (open-drain).
SCL — I
only if I
register.
PIO0_5 — General purpose digital input/output pin (open-drain).
SDA — I
only if I
register.
PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
PIO0_8 — General purpose digital input/output pin.
MISO0 — Master In Slave Out for SPI0.
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
C-bus pins
2
2
C Fast-mode Plus is selected in the I/O configuration
C Fast-mode Plus is selected in the I/O configuration
2
2
C-bus, open-drain clock input/output. High-current sink
C-bus, open-drain data input/output. High-current sink
002aag596
20
19
18
17
16
15
14
13
12
11
PIO0_4/SCL
PIO0_2/SSEL0/CT16B0_CAP0
PIO0_1/CLKOUT/CT32B0_MAT2
RESET/PIO0_0
V
V
XTALIN
XTALOUT
PIO1_7/TXD/CT32B0_MAT1
PIO1_6/RXD/CT32B0_MAT0
SS
DD
2
C-bus pins)
UM10398
© NXP B.V. 2012. All rights reserved.
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