LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 518

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 160. LPC1111/12/13/14 pin description table
Table 161. LPC1112FHN24 Pin description table (HVQFN24
Table 162. LPC11C24/C22 pin description table (LQFP48
Table 163. LPC11D14 pin description table (LQFP100
Table 164. LPC11xx pin configurations for 20-pin and 28-pin
Table 165. LPC1110/11/12 pin description table (SO20 and
Table 166. LPC1112 pin description table (TSSOP20 with
Table 167. LPC1112/14 pin description table (TSSOP28 and
Table 168. LPC1100XL pin configurations. . . . . . . . . . . .171
Table 169. LPC1113/14/15XL pin description table (LQFP48
Table 170. LPC1111/12/13/14XL pin description table
Table 171. GPIO configuration . . . . . . . . . . . . . . . . . . . .183
Table 172. Register overview: GPIO (base address port 0:
Table 173. GPIOnDATA register (GPIO0DATA, address
Table 174. GPIOnDIR register (GPIO0DIR, address 0x5000
Table 175. GPIOnIS register (GPIO0IS, address 0x5000
Table 176. GPIOnIBE register (GPIO0IBE, address 0x5000
Table 177. GPIOnIEV register (GPIO0IEV, address 0x5000
Table 178. GPIOnIE register (GPIO0IE, address 0x5000
Table 179. GPIOnRIS register (GPIO0RIS, address 0x5000
Table 180. GPIOnMIS register (GPIO0MIS, address 0x5000
Table 181. GPIOnIC register (GPIO0IC, address 0x5000
Table 182. UART pin description . . . . . . . . . . . . . . . . . . .191
Table 183. Register overview: UART (base address: 0x4000
UM10398
User manual
(HVQFN33 package) . . . . . . . . . . . . . . . . . .147
package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
package) . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
TSSOP20 package with I
V
DIP28 packages) . . . . . . . . . . . . . . . . . . . . . .168
package) . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
(HVQFN33 package) . . . . . . . . . . . . . . . . . .179
0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002
0000; port 3: 0x5003 0000) . . . . . . . . . . . . . .184
0x5000 0000 to 0x5000 3FFC; GPIO1DATA,
address 0x5001 0000 to 0x5001 3FFC;
GPIO2DATA, address 0x5002 0000 to 0x5002
3FFC; GPIO3DATA, address 0x5003 0000 to
0x5003 3FFC) bit description . . . . . . . . . . . .184
8000 to GPIO3DIR, address 0x5003 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .185
8004 to GPIO3IS, address 0x5003 8004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .185
8008 to GPIO3IBE, address 0x5003 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .186
800C to GPIO3IEV, address 0x5003 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .186
8010 to GPIO3IE, address 0x5003 8010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .186
8014 to GPIO3RIS, address 0x5003 8014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .187
8018 to GPIO3MIS, address 0x5003 8018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .187
801C to GPIO3IC, address 0x5003 801C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .187
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
DDA
and V
SSA
pins) . . . . . . . . . . . . . . . . . . .165
2
C-bus pins) . . . . . .162
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Table 184. UART Receiver Buffer Register (U0RBR -
Table 185. UART Transmitter Holding Register (U0THR -
Table 186. UART Divisor Latch LSB Register (U0DLL -
Table 187. UART Divisor Latch MSB Register (U0DLM -
Table 188. UART Interrupt Enable Register (U0IER -
Table 189. UART Interrupt Identification Register (U0IIR -
Table 190. UART Interrupt Handling . . . . . . . . . . . . . . . . 196
Table 191. UART FIFO Control Register (U0FCR - address
Table 192. UART Line Control Register (U0LCR - address
Table 193. UART0 Modem Control Register (U0MCR -
Table 194. Modem status interrupt generation . . . . . . . . 201
Table 195. UART Line Status Register (U0LSR - address
Table 196. UART Modem Status Register (U0MSR - address
Table 197. UART Scratch Pad Register (U0SCR - address
Table 198. Auto baud Control Register (U0ACR - address
Table 199. UART Fractional Divider Register (U0FDR -
Table 200. Fractional Divider setting look-up table . . . . . 211
Table 201. UART Transmit Enable Register (U0TER -
Table 202. UART RS485 Control register (U0RS485CTRL -
Table 203. UART RS485 Address Match register
Table 204. UART RS485 Delay value register (U0RS485DLY
Table 205. SPI pin descriptions . . . . . . . . . . . . . . . . . . . 218
Table 206. Register overview: SPI0 (base address 0x4004
Table 207. Register overview: SPI1 (base address 0x4005
Table 208: SPI/SSP Control Register 0 (SSP0CR0 - address
Table 209: SPI/SSP Control Register 1 (SSP0CR1 - address
Table 210: SPI/SSP Data Register (SSP0DR - address
address 0x4000 8000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . 193
address 0x4000 8000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . 193
address 0x4000 8000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
address 0x4000 8004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
address 0x4000 8004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 194
address 0x4004 8008, Read Only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 195
0x4000 8008, Write Only) bit description . . . . 198
0x4000 800C) bit description . . . . . . . . . . . . 198
address 0x4000 8010) bit description . . . . . . 199
0x4000 8014, Read Only) bit description . . . 202
0x4000 8018) bit description . . . . . . . . . . . . . 204
0x4000 801C) bit description . . . . . . . . . . . . . 204
0x4000 8020) bit description . . . . . . . . . . . . . 205
address 0x4000 8028) bit description . . . . . . 208
address 0x4000 8030) bit description . . . . . . 212
address 0x4000 804C) bit description . . . . . 212
(U0RS485ADRMATCH - address 0x4000 8050)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 213
- address 0x4000 8054) bit description . . . . . 213
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
0x4004 0000, SSP1CR0 - address 0x4005 8000)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 220
0x4004 0004, SSP1CR1 - address 0x4005 8004)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 221
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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