LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 50

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.11.2 Power-down control
3.11.3 Divider ratio programming
3.11.4 Frequency selection
row to be below a certain figure ensures that the lock detector will not indicate lock until
both the phase and frequency of the input and feedback clocks are very well aligned. This
effectively prevents false lock indications, and thus ensures a glitch free lock signal.
To reduce the power consumption when the PLL clock is not needed, a Power-down
mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bits to one
in the Power-down configuration register
reference will be turned off, the oscillator and the phase-frequency detector will be
stopped and the dividers will enter a reset state. While in Power-down mode, the lock
output will be low to indicate that the PLL is not in lock. When the Power-down mode is
terminated by setting the SYSPLL_PD bits to zero, the PLL will resume its normal
operation and will make the lock signal high once it has regained lock on the input clock.
Post divider
The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two
times the value of P selected by PSEL bits as shown in
output clock with a 50% duty cycle.
Feedback divider
The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio
between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus
one, as specified in
Changing the divider values
Changing the divider ratio while the PLL is running is not recommended. As there is no
way to synchronize the change of the MSEL and PSEL values with the dividers, the risk
exists that the counter will read in an undefined value, which could lead to unwanted
spikes or drops in the frequency of the output clock. The recommended way of changing
between divider settings is to power down the PLL, adjust the divider settings and then let
the PLL start up again.
The PLL frequency equations use the following parameters (also see
Table 45.
Parameter
FCLKIN
FCCO
FCLKOUT
P
M
PLL frequency parameters
All information provided in this document is subject to legal disclaimers.
System PLL
Frequency of sys_pllclkin (input clock to the system PLL) from the
SYSPLLCLKSEL multiplexer (see
Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.
Frequency of sys_pllclkout. FCLKOUT must be < 100 MHz.
System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see
System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see
Section
Table
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.3).
10.
(Table
43). In this mode, the internal current
Section
Table
3.5.9).
10. This guarantees an
Figure
UM10398
© NXP B.V. 2012. All rights reserved.
Section
8):
50 of 538
3.5.3).