LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 64

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

6.1 How to read this chapter
6.2 Introduction
6.3 Features
6.4 Interrupt sources
UM10398
User manual
The C_CAN controller interrupt is available on parts LPC11Cxx only.
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
Table 54
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about what
line is connected where, except for certain standards from ARM.
See
Table 54.
Exception
Number
12 to 0
13
14
15
•
•
•
•
•
•
UM10398
Chapter 6: LPC111x/LPC11Cxx Nested Vectored Interrupt
Controller (NVIC)
Rev. 12 — 24 September 2012
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0
Tightly coupled interrupt controller provides low interrupt latency
Controls system exceptions and peripheral interrupts
The NVIC supports 32 vectored interrupts
4 programmable interrupt priority levels with hardware priority level masking
Software interrupt generation
Section 28.6.2
lists the interrupt sources for each peripheral function. Each peripheral device
Connection of interrupt sources to the Vectored Interrupt Controller
Vector
Offset
All information provided in this document is subject to legal disclaimers.
for the NVIC register bit descriptions.
Rev. 12 — 24 September 2012
Function
start logic wake-up
interrupts
C_CAN
SPI/SSP1
I
2
C
Flag(s)
Each interrupt is connected to a PIO input pin serving
as wake-up pin from Deep-sleep mode; Interrupt 0 to
11 correspond to PIO0_0 to PIO0_11 and interrupt
12 corresponds to PIO1_0; see
C_CAN interrupt
Tx FIFO half empty
Rx FIFO half full
Rx Timeout
Rx Overrun
SI (state change)
Section
© NXP B.V. 2012. All rights reserved.
User manual
3.5.29.
64 of 538