LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 507

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.6.3.7.2 System Handler Priority Register 3
28.6.3.8 SCB usage hints and tips
28.6.4 System timer, SysTick
Table 455. SHPR2 register bit assignments
The bit assignments are:
Table 456. SHPR3 register bit assignments
Ensure software uses aligned 32-bit word size transactions to access all the SCB
registers.
When enabled, the timer counts down from the current value (SYST_CVR) to zero,
reloads (wraps) to the value in the SysTick Reload Value Register (SYST_RVR) on the
next clock edge, then decrements on subsequent clocks. When the counter transitions to
zero, the COUNTFLAG status bit is set to 1. The COUNTFLAG bit clears on reads.
Remark: The SYST_CVR value is UNKNOWN on reset. Software should write to the
register to clear it to zero before enabling the feature. This ensures the timer will count
from the SYST_RVR value rather than an arbitrary value when it is enabled.
Remark: If the SYST_RVR is zero, the timer will be maintained with a current value of
zero after it is reloaded with this value. This mechanism can be used to disable the feature
independently from the timer enable bit.
A write to the SYST_CVR will clear the register and the COUNTFLAG status bit. The write
causes the SYST_CVR to reload from the SYST_RVR on the next timer clock, however, it
does not trigger the SysTick exception logic. On a read, the current value is the value of
the register at the time the register is accessed.
Remark: When the processor is halted for debugging the counter does not decrement.
The system timer registers are:
Table 457. System timer registers summary
[1]
Bits
[31:24]
[23:0]
Bits
[31:24]
[23:16]
[15:0]
Address
0xE000E010
0xE000E014
0xE000E018
0xE000E01C
SysTick calibration value.
Name
PRI_15
PRI_14
-
Name
SYST_CSR
SYST_RVR
SYST_CVR
SYST_CALIB RO
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Name
PRI_11
-
Rev. 12 — 24 September 2012
Function
Priority of system handler 15, SysTick exception
Priority of system handler 14, PendSV
Reserved
Type
RW
RW
RW
Function
Priority of system handler 11, SVCall
Reserved
Reset
value
0x00000000
Unknown
Unknown
0x00000004
[1]
Description
Section 28.6.4.1
Section 28–28.6.4.2
Section 28–28.6.4.3
Section 28–28.6.4.4
UM10398
© NXP B.V. 2012. All rights reserved.
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