LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 462

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.4.4.1 Lockup
28.4.4 Fault handling
not a normal branch operation and, instead, that the exception is complete. Therefore, it
starts the exception return sequence. Bits[3:0] of the EXC_RETURN value indicate the
required return stack and processor mode, as
Table 428. Exception return behavior
Faults are a subset of exceptions, see
exception being taken or cause lockup if they occur in the NMI or HardFault handler. The
faults are:
Remark: Only Reset and NMI can preempt the fixed priority HardFault handler. A
HardFault can preempt any exception other than Reset, NMI, or another hard fault.
The processor enters a lockup state if a fault occurs when executing the NMI or HardFault
handlers, or if the system generates a bus error when unstacking the PSR on an
exception return using the MSP. When the processor is in lockup state it does not execute
any instructions. The processor remains in lockup state until one of the following occurs:
EXC_RETURN
0xFFFFFFF1
0xFFFFFFF9
0xFFFFFFFD
All other values
•
•
•
•
•
•
•
•
•
•
•
•
execution of an SVC instruction at a priority equal or higher than SVCall
execution of a BKPT instruction without a debugger attached
a system-generated bus error on a load or store
execution of an instruction from an XN memory address
execution of an instruction from a location for which the system generates a bus fault
a system-generated bus error on a vector fetch
execution of an Undefined instruction
execution of an instruction when not in Thumb-State as a result of the T-bit being
previously cleared to 0
an attempted load or store to an unaligned address.
it is reset
a debugger halts it
an NMI occurs and the current lockup is in the HardFault handler.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Description
Return to Handler mode.
Exception return gets state from the main stack.
Execution uses MSP after return.
Return to Thread mode.
Exception return gets state from MSP.
Execution uses MSP after return.
Return to Thread mode.
Exception return gets state from PSP.
Execution uses PSP after return.
Reserved.
Rev. 12 — 24 September 2012
Section
Table 28–428
28–28.4.3. All faults result in the HardFault
shows.
UM10398
© NXP B.V. 2012. All rights reserved.
462 of 538