LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 226

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
Fig 37. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)
a. Single transfer with CPOL=0 and CPHA=0
b. Continuous transfer with CPOL=0 and CPHA=0
SSEL
MOSI
MISO
SCK
14.7.2.2 SPI format with CPOL=0,CPHA=0
MSB
MSB
The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing a
clock transition before the first data capture edge. When the CPHA phase control bit is
LOW, data is captured on the first clock edge transition. If the CPHA clock phase control
bit is HIGH, data is captured on the second clock edge transition.
Single and continuous transmission signal sequences for SPI format with CPOL = 0,
CPHA = 0 are shown in
In this configuration, during idle periods:
If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. This causes slave
data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled.
One half SCK period later, valid master data is transferred to the MOSI pin. Now that both
the master and slave data have been set, the SCK master clock pin goes HIGH after one
further half SCK period.
The data is captured on the rising and propagated on the falling edges of the SCK signal.
•
•
•
The CLK signal is forced LOW.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance.
SSEL
MOSI
MISO
SCK
4 to 16 bits
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
MSB
LSB
LSB
MSB
Figure
Q
37.
4 to 16 bits
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
MSB
MSB
LSB
LSB
Q
4 to 16 bits
UM10398
© NXP B.V. 2012. All rights reserved.
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