LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 491

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.7.2.3 Restrictions
28.5.7.2.4 Condition flags
28.5.7.2.5 Examples
28.5.7.3.1 Syntax
28.5.7.3.2 Operation
28.5.7.3.3 Restrictions
28.5.7.3.4 Condition flags
28.5.7.3.5 Examples
28.5.7.4.1 Syntax
28.5.7.4.2 Operation
28.5.7.4.3 Restrictions
28.5.7.3 DMB
28.5.7.4 DSB
There are no restrictions.
This instruction does not change the condition flags.
Data Memory Barrier.
DMB
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that
appear in program order before the DMB instruction are observed before any explicit
memory accesses that appear in program order after the DMB instruction. DMB does not
affect the ordering of instructions that do not access memory.
There are no restrictions.
This instruction does not change the flags.
Data Synchronization Barrier.
DSB
DSB acts as a special data synchronization memory barrier. Instructions that come after
the DSB, in program order, do not execute until the DSB instruction completes. The DSB
instruction completes when all explicit memory accesses before it complete.
There are no restrictions.
CPSID i ; Disable all interrupts except NMI (set PRIMASK)
CPSIE i ; Enable interrupts (clear PRIMASK)
DMB ; Data Memory Barrier
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
UM10398
© NXP B.V. 2012. All rights reserved.
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