LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 29

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.13 System AHB clock divider register
3.5.14 System AHB clock control register
Table 19.
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0.
Table 20.
The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.
The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock
for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the Syscon block, and
the PMU. This clock cannot be disabled.
Table 21.
Bit
0
31:1
Bit
7:0
31:8
Bit
0
1
2
3
Symbol
ENA
-
Symbol
DIV
-
Symbol
SYS
ROM
RAM
FLASHREG
Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)
bit description
System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit
description
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
All information provided in this document is subject to legal disclaimers.
System AHB clock divider values
Description
0: System clock disabled.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Value
0
1
-
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Value
0
1
0
1
0
1
0
1
Description
Enable main clock source update
No change
Update clock source
Reserved
Description
Enables clock for AHB to APB bridge, to the AHB
matrix, to the Cortex-M0 FCLK and HCLK, to the
SysCon, and to the PMU. This bit is read only.
Reserved
Enable
Enables clock for ROM.
Disable
Enable
Enables clock for RAM.
Disable
Enable
Enables clock for flash register interface.
Disabled
Enabled
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0x01
0x00
Reset value
0x0
0x00
29 of 538
Reset
value
1
1
1
1