LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 299

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.7.2.4.1 Silent mode
16.7.2.4.2 Loop-back mode
16.7.2.4 Test modes
The Disable Automatic Retransmission mode is enabled by programming bit DAR in the
CAN Control Register to one. In this operation mode the programmer has to consider the
different behavior of bits TXRQST and NEWDAT in the Control Registers of the Message
Buffers:
The Test mode is entered by setting bit TEST in the CAN Control Register to one. In Test
mode the bits TX1, TX0, LBACK, SILENT, and BASIC in the Test Register are writable. Bit
RX monitors the state of pins RD0,1 and therefore is only readable. All Test register
functions are disabled when bit TEST is reset to zero.
The CAN core can be set in Silent mode by programming the Test register bit SILENT to
one.
In Silent Mode, the CAN controller is able to receive valid data frames and valid remote
frames, but it sends only recessive bits on the CAN bus, and it cannot start a
transmission. If the CAN Core is required to send a dominant bit (ACK bit, overload flag,
active error flag), the bit is rerouted internally so that the CAN Core monitors this dominant
bit, although the CAN bus may remain in recessive state. The Silent mode can be used to
analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits
(Acknowledge Bits, Error Frames).
The CAN Core can be set in Loop-back mode by programming the Test Register bit
LBACK to one. In Loop-back Mode, the CAN Core treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into a Receive
Buffer.
Fig 61. CAN core in Silent mode
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•
•
When a transmission starts, bit TXRQST of the respective Message Buffer is reset
while bit NEWDAT remains set.
When the transmission completed successfully, bit NEWDAT is reset.
When a transmission failed (lost arbitration or error), bit NEWDAT remains set. To
restart the transmission, the CPU has to set TXRQST back to one.
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
C_CAN
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
CAN_TXD CAN_RXD
= 1
Rx
CAN CORE
Tx
UM10398
© NXP B.V. 2012. All rights reserved.
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