LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 263

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
Fig 56. Format and states in the Slave Transmitter mode
15.10.5.1 STAT = 0xF8
15.10.5.2 STAT = 0x00
15.10.5 Miscellaneous states
reception of the own
Slave address and
one or more Data
bytes all are
acknowledged
last data byte
transmitted. Switched
to Not Addressed
Slave (AA bit in
I2CON = “0”)
arbitration lost as
Master and
addressed as Slave
DATA
n
There are two STAT codes that do not correspond to a defined I
Table
This status code indicates that no relevant information is available because the serial
interrupt flag, SI, is not yet set. This occurs between other states and when the I
is not involved in a serial transfer.
This status code indicates that a bus error has occurred during an I
bus error is caused when a START or STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. A bus error may also be caused when
external interference disturbs the internal I
set. To recover from a bus error, the STO flag must be set and SI must be cleared. This
A
241). These are discussed below.
S
from Master to Slave
from Slave to Master
any number of data bytes and their associated
Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of
the I
2
C bus
SLA
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
R
A8H
B0H
A
A
DATA
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
B8H
2
A
C block signals. When a bus error occurs, SI is
DATA
C8H
C0H
A
A
P OR S
ALL ONES
2
C hardware state (see
2
C serial transfer. A
UM10398
P OR S
© NXP B.V. 2012. All rights reserved.
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C block