S1D13A04F00A Epson Electronics America Inc-Semiconductor Div, S1D13A04F00A Datasheet
S1D13A04F00A
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S1D13A04 LCD/USB Companion Chip S1D13A04 TECHNICAL MANUAL Document Number: X37A-Q-001-01 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only ...
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Page 2 S1D13A04 X37A-Q-001-01 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 01/10/02 ...
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Epson Research and Development Vancouver Design Center COMPREHENSIVE SUPPORT TOOLS EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems. Documentation • Technical manuals • Evaluation/Demonstration board manual Evaluation/Demonstration Board ...
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Page 4 S1D13A04 X37A-Q-001-01 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 01/10/02 ...
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ENERGY EPSON S1D13A04 LCD/USB Companion Chip The S1D13A04 is an LCD/USB solution designed for seamless connection to a wide variety of micro- processors. The S1D13A04 integrates a USB slave controller and an LCD graphics controller ...
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GRAPHICS S1D13A04 DESCRIPTION CPU Interface • ‘Fixed’ low-latency CPU access times. • Direct support for: Hitachi SH-4 / SH-3. Motorola M68xxx (REDCAP2, DragonBall, ColdFire) MPU bus interface with programmable READY. Memory Interface • Embedded 160K byte SRAM display buffer. Power ...
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S1D13A04 LCD/USB Companion Chip Hardware Functional Specification Document Number: X37A-A-001-06 Status: Revision 6.0 Issue Date: 2003/05/01 Copyright © 2001, 2003 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may ...
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Page 2 S1D13A04 X37A-A-001-06 THIS PAGE LEFT BLANK Revision 6.0 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2003/05/01 ...
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Epson Research and Development Vancouver Design Center 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Page 4 6.2.3 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2.4 Hitachi SH-4 Interface ...
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Epson Research and Development Vancouver Design Center 8.3.3 Panel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Page 6 S1D13A04 X37A-A-001-06 THIS PAGE LEFT BLANK Revision 6.0 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2003/05/01 ...
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Epson Research and Development Vancouver Design Center Table 4-1: PFBGA 121-pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Page 8 Table 6-26: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Epson Research and Development Vancouver Design Center Figure 3-1: Typical System Diagram (Generic #1 Bus ...
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Page 10 Figure 6-27: Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Epson Research and Development Vancouver Design Center 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13A04 LCD/USB Companion Chip. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. ...
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Page 12 2 Features 2.1 Integrated Frame Buffer • Embedded 160k byte SRAM display buffer. 2.2 CPU Interface • Direct support of the following interfaces: Generic MPU bus interface with programmable ready (WAIT#). Hitachi SH-4 / SH-3. Motorola M68K. Motorola ...
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Epson Research and Development Vancouver Design Center 2.5 Display Features • SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image. • Virtual display support: displays images larger than the panel size through the use of panning and scrolling. • ...
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Page 14 2.9 Miscellaneous • Software Video Invert. • Software initiated Power Save mode. • General Purpose Input/Output pins are available. • IO Operates at 3.3 volts • Core operates at 2.0 volts • 121-pin PFBGA package. • 128-pin TQFP15 ...
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Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams 3.1 Typical System Diagrams. Generic #1 IOVDD BUS VSS A[27:18] Decoder CSn# A[17:1] D[15:0] WE0# WE1# RD0# RD1# WAIT# BUSCLK RESET# Figure 3-1: Typical System Diagram (Generic #1 ...
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Page 16 SH-4 BUS VSS A[25:18] Decoder CSn# A[17:1] D[15:0] WE0# WE1# BS# RD/WR# RD# RDY# CKIO RESET# Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus) SH-3 BUS VSS A[25:18] Decoder CSn# A[17:1] D[15:0] WE0# WE1# BS# RD/WR# RD# WAIT# ...
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Epson Research and Development Vancouver Design Center MC68K #1 BUS IOVDD A[23:18] Decoder FC0, FC1 Decoder A[17:1] D[15:0] LDS# UDS# AS# R/W# DTACK# CLK RESET# Figure 3-5: Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000) MC68K #2 BUS A[31:18] ...
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Page 18 REDCAP2 BUS IOVDD A[21:18] Decoder CSn A[17:1] D[15:0] R/W OE EB1 EB0 CLK RESET_OUT VSS *Note: CSn# can be any of CS0-CS4 Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus) MC68EZ328/ MC68VZ328 IOVDD DragonBall BUS A[25:18] Decoder CSX ...
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Epson Research and Development Vancouver Design Center 3.2 USB Interface S1D13A04 USBDETECT USBPUP USBDP USBDM VSS Hardware Functional Specification Issue Date: 2003/05/01 150k 300k Full Speed Device LVDD 1. 300k NNCD5.6LG Overvoltage Protection ESD Protection Figure 3-9: USB ...
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Page 20 4 Pins 4.1 Pinout Diagram - PFBGA - 121-pin Figure 4-1: Pinout Diagram - PFBGA 121-pin L NC IOVDD DB7 K NC VSS DB8 J NC DB9 ...
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Epson Research and Development Vancouver Design Center 4.2 Pinout Diagram - TQFP15 - 128-pin IOVDD CLKI2 100 PWMOUT 101 NC 102 CNF6 ...
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Page 22 4.3 Pin Descriptions Key Input O = Output IO = Bi-Directional (Input/Output Power pin CI = CMOS input LI = LVTTL input LB2A = LVTTL IO buffer (6mA/-6mA@3.3V) LB3P = Low noise LVTTL IO ...
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Epson Research and Development Vancouver Design Center PFBGA TQFP15 Pin Name Type Pin # Pin# L5,K5,J5, L4,K4,J4, J3,L3,K3, 23-29, DB[15:0] IO J2,H3,H2, 35-43 H1,H4,G3 ,G2 WE0 WE1 CS Hardware Functional Specification ...
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Page 24 PFBGA TQFP15 Pin Name Type Pin # Pin RD/WR RD S1D13A04 X37A-A-001-06 Table 4-2: Host Interface Pin Descriptions RESET# Cell State This input pin ...
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Epson Research and Development Vancouver Design Center PFBGA TQFP15 Pin Name Type Pin # Pin# WAIT RESET Hardware Functional Specification Issue Date: 2003/05/01 Table 4-2: Host Interface Pin Descriptions RESET# Cell State During a ...
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Page 26 4.3.2 LCD Interface PFBGA TQFP15 Pin Name Type Pin# Pin# C10,D9,D 10,D,11,D 8,E9,E10, E11,E8,F 71-77, FPDAT[17:0] O 7,F10,F8, 82-92 G7,G11,G 10,G9,G8 ,H11 FPFRAME FPLINE FPSHIFT O H10 70 DRDY ...
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Epson Research and Development Vancouver Design Center PFBGA TQFP15 Pin Name Type Pin# Pin# GPIO1 GPIO2 GPIO3 GPIO4 Hardware Functional Specification Issue Date: 2003/05/01 Table 4-3: LCD Interface ...
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Page 28 PFBGA TQFP15 Pin Name Type Pin# Pin# GPIO5 GPIO6 GPIO7 IRQ PWMOUT O A9 100 S1D13A04 X37A-A-001-06 Table 4-3: LCD Interface Pin Descriptions RESET# Cell State ...
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Epson Research and Development Vancouver Design Center 4.3.3 Clock Input PFBGA TQFP15 Pin Name Type Pin# Pin# CLKI CLKI2 USBCLK 4.3.4 Miscellaneous PFBGA TQFP15 Pin Name Type Pin# Pin# C9,C8,B8 CNF[6:0] ...
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Page 30 4.4 Summary of Configuration Options These pins are used for configuration of the S1D13A04 and must be connected directly to IOV state at any other time has no effect. Table 4-7: Summary of Power-On/Reset Options ...
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Epson Research and Development Vancouver Design Center 4.5 Host Bus Interface Pin Mapping S1D13A04 Generic #1 Generic #2 Pin Name AB[17:1] A[17:1] A[17:1] 1 AB0 A0 DB[15:0] D[15:0] D[15:0] CS# External Decode M/R# CLKI BUSCLK BUSCLK BS# Connected to IO ...
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Page 32 4.6 LCD Interface Pin Mapping Monochrome Passive Panel Pin Name Single 4-bit 8-bit FPFRAME FPLINE FPSHIFT DRDY MOD FPDAT0 driven 0 D0 driven 0 FPDAT1 driven 0 D1 driven 0 FPDAT2 driven 0 D2 driven 0 FPDAT3 driven ...
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Epson Research and Development Vancouver Design Center 5 D.C. Characteristics Note When applying Supply Voltages to the S1D13A04, Core V chip before, or simultaneously with IO V Symbol Parameter Core V Supply Voltage Supply Voltage DD V ...
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Page 34 6 A.C. Characteristics Conditions - and T rise C = 50pF (Bus/MPU Interface 0pF (LCD Panel Interface) L 6.1 Clock Timing 6.1.1 Input Clocks Clock ...
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Epson Research and Development Vancouver Design Center Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1 Symbol f Input Clock Frequency (CLKI) OSC T Input Clock period (CLKI) OSC t Input Clock Pulse Width High ...
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Page 36 6.2 CPU Interface Timing 6.2.1 Generic #1 Interface Timing (e.g. Epson EOC33) CLK A[16:1], M/R# CS# WE0#, WE1#, RD0#, RD1# WAIT# D[15:0] (write) D[15:0] (read) S1D13A04 X37A-A-001-06 T CLK t1 t2 t14 valid t5 Figure ...
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Epson Research and Development Vancouver Design Center Symbol f Bus clock frequency CLK T Bus clock period CLK A[16:1], M/R# setup to first CLK rising edge where CS and t1 either RD0#, RD1 WE0#, WE1# ...
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Page 38 6.2.2 Generic #2 Interface Timing (e.g. ISA) BUSCLK A[16:0], M/R#, BHE# CS# WE#, RD# WAIT# D[15:0] (write) D[15:0] (read) S1D13A04 X37A-A-001-06 T BUSCLK t1 t2 t14 valid t5 Figure 6-3: Generic #2 Interface Timing Revision ...
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Epson Research and Development Vancouver Design Center Symbol f Bus clock frequency BUSCLK T Bus clock period BUSCLK A[16:0], M/R#, BHE# setup to first BUSCLK rising edge where CS and either RD WE# = ...
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Page 40 6.2.3 Hitachi SH-3 Interface Timing CKIO A[16:1], M/R#, RD/WR# BS# CSn# WEn#, RD# WAIT# D[15:0] (write) D[15:0] (read) Note For this interface, the following formula must apply BCLK greater than 33MHz is desired, MCLK must be ...
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Epson Research and Development Vancouver Design Center Symbol f Bus clock frequency CKIO T Bus clock period CKIO t1 A[16:1], RD/WR# setup to CKIO t2 BS# setup t3 BS# hold t4 CSn# setup t5 WEn#, RD# setup to next CKIO ...
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Page 42 6.2.4 Hitachi SH-4 Interface Timing CKIO A[16:1], M/R#, RD/WR# BS# CSn# WEn#, RD# RDY# D[15:0] (write) D[15:0] (read) S1D13A04 X37A-A-001-06 T CKIO t1 t19 valid t8 Figure 6-5: Hitachi SH-4 Interface Timing ...
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Epson Research and Development Vancouver Design Center Symbol f Bus clock frequency CKIO T Bus clock period CKIO t1 A[16:1], M/R#, RD/WR# setup to CKIO t2 BS# setup t3 BS# hold t4 CSn# setup t5 WEn#, RD# setup to 2nd ...
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Page 44 6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000) T CLK CLK t1 A[16:1], R/W#, M/R# t1 CS# t1 AS# t1 UDS#, LDS#, (A0) DTACK# D[15:0] (write) t3 D[15:0] (read) Figure 6-6: Motorola MC68K #1 Interface Timing S1D13A04 X37A-A-001-06 ...
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Epson Research and Development Vancouver Design Center Table 6-12: Motorola MC68K#1 Interface Timing Symbol f Bus clock frequency CLK T Bus clock period CLK A[16:1], M/R#, R/W# and CS# and AS# and UDS#, LDS# setup to t1 first CLK rising ...
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Page 46 6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030) CLK A[16:1], M/R#, R/W#, SIZ[1:0] CS# AS# DS# DSACK1# D[31:16] (write) D[31:16] (read) Figure 6-7: Motorola MC68K #2 Interface Timing S1D13A04 X37A-A-001-06 T CLK t12 ...
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Epson Research and Development Vancouver Design Center Table 6-13: Motorola MC68K#2 Interface Timing Symbol f Bus clock frequency CLK T Bus clock period CLK A[16:0], M/R#, R/W#, SIZ[1:0] and CS# and AS# and DS# setup to t1 first CLK rising ...
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Page 48 6.2.7 Motorola REDCAP2 Interface Timing T CKO CKO t1 A[16:1], R/W#, CS# t2 EBO#, EB1# (write) D[15:0] (write) t5 EB0#, EB1#, OE# (read) t7 D[15:0] (read) Figure 6-8: Motorola Redcap2 Interface Timing S1D13A04 X37A-A-001-06 t12 t3 t4 valid ...
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Epson Research and Development Vancouver Design Center Symbol f Bus clock frequency CKO T Bus clock period CKO t1 A[16:1], R/W, CSn# setup to CKO rising edge t2 EB0,EB1 setup to CKO rising edge (write) D[15:0] input setup to 4th ...
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Page 50 6.2.8 Motorola Dragonball Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328) CLKO t1 A[16:1] t1 CSX t1 UWE, LWE (write (read) D[15:0] (write) t2 D[15:0] (read) t3 DTACK Figure 6-9: Motorola Dragonball Interface Timing with DTACK S1D13A04 X37A-A-001-06 ...
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Epson Research and Development Vancouver Design Center Table 6-15: Motorola Dragonball Interface Timing with DTACK Symbol f Clock frequency CLKO T Clock period CLKO t1 A[16:1], CSX, UWE, LWE, OE setup to CLKO rising edge t2 CSX and OE asserted ...
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Page 52 6.2.9 Motorola Dragonball Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328) CLKO t1 A[16:1] t1 CSX# t1 UWE#, LWE# (write) t1 OE# (read) D[15:0] (write) t3 D[15:0] (read) Figure 6-10: Motorola Dragonball Interface Timing w/o DTACK S1D13A04 X37A-A-001-06 T CLKO ...
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Epson Research and Development Vancouver Design Center Table 6-16: Motorola Dragonball Interface Timing w/o DTACK Symbol f Bus clock frequency CLKO T Bus clock period CLKO A[16:1] and CSX# and UWE#, LWE# and OE# setup to CLKO t1 rising edge ...
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Page 54 6.3 LCD Power Sequencing 6.3.1 Passive/TFT Power-On Sequence GPIO0* Power Save Mode Enable** (REG[A0h] bit 0) LCD Signals*** *It is recommended to use the general purpose IO pin GPIO0 to control the LCD bias power. **The LCD power-on ...
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Epson Research and Development Vancouver Design Center 6.3.2 Passive/TFT Power-Off Sequence GPIO0* Power Save Mode Enable** (REG[A0h] bit 0) LCD Signals*** *It is recommended to use the general purpose IO pin GPIO0 to control the LCD bias power. **The LCD ...
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Page 56 6.4 Display Interface The timing parameters required to drive a flat panel display are shown below. Timing details for each supported panel type are provided in the remainder of this section. HDPS VPS VDPS VPW VT S1D13A04 X37A-A-001-06 ...
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Epson Research and Development Vancouver Design Center Table 6-19: Panel Timing Parameter Definition and Register Summary Symbol Description HT Horizontal Total 1 HDP Horizontal Display Period HDPS Horizontal Display Period Start Position HPS FPLINE Pulse Start Position HPW FPLINE Pulse ...
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Page 58 6.4.1 Generic STN Panel Timing VPW FPFRAME FPLINE 1 MOD (DRDY) FPDAT[17:0] FPLINE FPSHIFT 1PCLK 2 MOD (DRDY) HDPS FPDAT[17:0] S1D13A04 X37A-A-001- Frame) VDP Line) HPS HDP Figure 6-14: Generic STN Panel ...
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Epson Research and Development Vancouver Design Center VT = Vertical Total VPS = FPFRAME Pulse Start Position VPW = FPFRAME Pulse Width VDPS = Vertical Display Period Start Position VDP = Vertical Display Period HT = Horizontal Total HPS = ...
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Page 60 6.4.2 Single Monochrome 4-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Invalid FPLINE DRDY (MOD) FPSHIFT FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Invalid * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 ...
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Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 6-16: Single Monochrome 4-Bit Panel A.C. Timing Table 6-20: Single Monochrome 4-Bit Panel A.C. Timing Symbol t1 FPFRAME setup to FPLINE ...
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Page 62 6.4.3 Single Monochrome 8-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Invalid FPLINE DRDY (MOD) FPSHIFT FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Invalid FPDAT3 Invalid FPDAT2 Invalid FPDAT1 Invalid FPDAT0 Invalid * Diagram drawn with 2 FPLINE ...
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Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 6-18: Single Monochrome 8-Bit Panel A.C. Timing Table 6-21: Single Monochrome 8-Bit Panel A.C. Timing Symbol t1 FPFRAME setup to FPLINE ...
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Page 64 6.4.4 Single Color 4-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Invalid FPLINE DRDY (MOD) .5Ts FPSHIFT Invalid FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Notes: - FPSHIFT uses extended low states in order to process 8 pixels ...
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Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 6-20: Single Color 4-Bit Panel A.C. Timing Table 6-22: Single Color 4-Bit Panel A.C. Timing Symbol t1 FPFRAME setup to FPLINE ...
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Page 66 6.4.5 Single Color 8-Bit Panel Timing (Format 1) FPFRAME FPLINE FPDAT[7:0] Invalid FPLINE 2Ts FPSHIFT FPSHIFT2 FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Invalid FPDAT3 Invalid FPDAT2 Invalid FPDAT1 Invalid FPDAT0 Invalid Notes: - The duty cycle of ...
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Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT FPSHIFT2 FPDAT[7:0] Figure 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1) Table 6-23: Single Color 8-Bit Panel A.C. Timing (Format 1) Symbol t1 FPFRAME ...
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Page 68 6.4.6 Single Color 8-Bit Panel Timing (Format 2) FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Invalid FPLINE DRDY (MOD) 2Ts FPSHIFT FPDAT7 Invalid 1-R1 FPDAT6 Invalid 1-G1 FPDAT5 Invalid 1-B1 FPDAT4 Invalid 1-R2 FPDAT3 Invalid 1-G2 FPDAT2 Invalid 1-B2 Invalid ...
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Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 6-24: Single Color 8-Bit Panel A.C. Timing (Format 2) Table 6-24: Single Color 8-Bit Panel A.C. Timing (Format 2) Symbol t1 ...
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Page 70 6.4.7 Single Color 16-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] Invalid FPLINE DRDY (MOD) 3Ts FPSHIFT Invalid 1-R1 FPDAT15 Invalid 1-B1 FPDAT14 Invalid FPDAT13 1-G2 Invalid FPDAT12 1-R3 FPDAT7 Invalid 1-B3 FPDAT6 Invalid 1-G4 FPDAT5 Invalid 1-R5 ...
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Epson Research and Development Vancouver Design Center Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[15:0] Figure 6-26: Single Color 16-Bit Panel A.C. Timing Table 6-25: Single Color 16-Bit Panel A.C. Timing Symbol t1 FPFRAME setup to FPLINE ...
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Page 72 6.4.8 Generic TFT Panel Timing VPS FPFRAME FPLINE DRDY FPDAT[17:0] HPS HPW FPLINE FPSHIFT DRDY HDPS FPDAT[17:0] invalid VT = Vertical Total VPS = FPFRAME Pulse Start Position VPW = FPFRAME Pulse Width VDPS = Vertical Display Period ...
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Epson Research and Development Vancouver Design Center 6.4.9 9/12/18-Bit TFT Panel Timing FPFRAME FPLINE FPDAT[17:0] LINE240 DRDY FPLINE FPSHIFT DRDY FPDAT[17:0] Note: DRDY is used to indicate the first pixel Example Timing for 18-bit 320x240 panel VDP = Vertical Display ...
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Page 74 FPFRAME t3 FPLINE FPLINE DRDY t9 t10 t11 FPSHIFT FPDAT[17:0] Note: DRDY is used to indicate the first pixel S1D13A04 X37A-A-001- t12 invalid Figure 6-29: TFT A.C. Timing Revision 6.0 Epson Research and Development Vancouver ...
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Epson Research and Development Vancouver Design Center Symbol FPFRAME cycle time t1 FPFRAME pulse width low t2 FPFRAME falling edge to FPLINE falling edge phase difference t3 FPLINE cycle time t4 FPLINE pulse width low t5 FPLINE Falling edge to ...
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Page 76 6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx) FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) t12 GPIO0 (PS) t13 GPIO2 (REV) Figure 6-30: 160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing S1D13A04 ...
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Epson Research and Development Vancouver Design Center Table 6-27: 160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing Symbol FPLINE start position t1 Horizontal total period t2 FPLINE width t3 FPSHIFT period t4 t5 Data setup to FPSHIFT rising edge t6 Data hold ...
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Page 78 FPDAT[17:0] t4 FPFRAME (SPS) GPIO1 (CLS) GPIO0 (PS) FPLINE (LP) FPSHIFT (CLK) GPIO1 (CLS) GPIO0 (PS) Figure 6-31: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing S1D13A04 X37A-A-001- LINE1 LINE2 t11 t12 t10 ...
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Epson Research and Development Vancouver Design Center Table 6-28: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing Symbol Vertical total period t1 Vertical display start position t2 Vertical display period t3 Vertical sync pulse width t4 FPFRAME falling edge to GPIO1 ...
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Page 80 6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) t12 GPIO0 (PS) t13 GPIO2 (REV) Figure 6-32: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing S1D13A04 ...
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Epson Research and Development Vancouver Design Center Table 6-29: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing Symbol FPLINE start position t1 Horizontal total period t2 FPLINE width t3 FPSHIFT period t4 t5 Data setup to FPSHIFT rising edge t6 Data ...
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Page 82 6.5 USB Timing Data Signal Rise and Fall Time Figure 6-36 Differential to EOP Transition Skew and EOP Width S1D13A04 X37A-A-001-06 Figure 6-34 Data Signal Rise and Fall Time Figure 6-35 Differential Data Jitter Revision 6.0 Epson Research ...
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Epson Research and Development Vancouver Design Center Symbol Parameter USB USB Clock Frequency FREQ T USB Clock Period PERIOD T R Rise & Fall Times Rise/Fall time matching RFM V Output Signal Crossover Voltage CRS Z Driver ...
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Page 84 7 Clocks 7.1 Clock Descriptions 7.1.1 BCLK BCLK is an internal clock derived from CLKI. BCLK can be a divided version ( CLKI. CLKI is typically derived from the host CPU bus clock. The source ...
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Epson Research and Development Vancouver Design Center 7.1.3 PCLK PCLK is the internal clock used to control the panel. It should be chosen to match the optimum frame rate of the panel. See Section 10, “Frame Rate Calculation” on page ...
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Page 86 There is a relationship between the frequency of MCLK and PCLK that must be maintained. SwivelView Orientation SwivelView 0° and 180° SwivelView 90° and 270° 7.1.4 PWMCLK PWMCLK is the internal clock used by the Pulse Width Modulator ...
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Epson Research and Development Vancouver Design Center 7.2 Clock Selection The following diagram provides a logical representation of the S1D13A04 internal clocks. USBCLK CLKI CLKI2 Note 1 CNF6 must be set at RESET#. Hardware Functional Specification Issue Date: 2003/05/01 0 ...
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Page 88 7.3 Clocks versus Functions Table 7-6: “S1D13A04 Internal Clock Requirements”, lists the internal clocks required for the following S1D13A04 functions. Table 7-6: S1D13A04 Internal Clock Requirements Bus Clock Function (BCLK) Register Read/Write Required Memory Read/Write Required Look-Up Table ...
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Epson Research and Development Vancouver Design Center 8 Registers This section discusses how and where to access the S1D13A04 registers. It also provides detailed information about the layout and usage of each register. 8.1 Register Mapping The S1D13A04 registers are ...
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Page 90 Register + REG[50h] PIP Window Display Start Address Register + REG[58h] PIP Window X Positions Register REG[60h] Special Purpose Register REG[70h] PWM Clock Configuration Register REG[80h] Scratch Pad A Register REG[88h] Scratch Pad C Register REG[4000h] Control Register ...
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Epson Research and Development Vancouver Design Center 8.3 LCD Register Descriptions (Offset = 0h) Unless specified otherwise, all register bits are set to 0 during power-on. 8.3.1 Read-Only Configuration Registers Product Information Register REG[00h] Default = 2Cxx282Ch Product Code bits ...
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Page 92 8.3.2 Clock Configuration Registers Memory Clock Configuration Register REG[04h] Default = 00000000h bits 5-4 MCLK Divide Select Bits [1:0] These bits determine the divide used to generate the ...
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Epson Research and Development Vancouver Design Center bits 1-0 PCLK Source Select Bits [1:0] These bits determine the source of the Pixel Clock (PCLK). PCLK Source Select Bits 8.3.3 Panel Configuration Registers Panel Type & MOD Rate Register REG[0Ch] Default ...
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Page 94 bit 3 ‘Direct’ HR-TFT Resolution Select This bit selects one of two panel resolutions when the ‘Direct’ HR-TFT interface is selected. This bit has no effect for other panel types. ‘Direct’ HR-TFT Resolution Select Bit bits 1-0 Panel ...
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Epson Research and Development Vancouver Design Center bit 23 Display Blank When this bit = 0, the LCD display pipeline is enabled. When this bit = 1, the LCD display pipeline is disabled and all LCD data outputs are forced ...
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Page 96 bits 4-0 Bit-per-pixel Select Bits [4:0] These bits select the color depth (bit-per-pixel) for the displayed data for both the main window and the PIP and 8 bpp modes use the 18-bit LUT, allowing maximum ...
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Epson Research and Development Vancouver Design Center bit 4 Power Save Mode Enable When this bit = 1, the software initiated power save mode is enabled. When this bit = 0, the software initiated power save mode is disabled. At ...
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Page 98 8.3.4 Look-Up Table Registers Look-Up Table Write Register REG[18h] Default = 00000000h LUT Write Address LUT Green Write Data Note The S1D13A04 has three 256-position, 6-bit wide LUTs, ...
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Epson Research and Development Vancouver Design Center Look-Up Table Read Register REG[1Ch] Default = 00000000h LUT Read Address (write only LUT Green Read Data Note The S1D13A04 has three 256-position, ...
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Page 100 8.3.5 Display Mode Registers Horizontal Total Register REG[20h] Default = 00000000h n bits 6-0 Horizontal Total Bits [6:0] These bits specify the LCD panel Horizontal Total period, in ...
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Epson Research and Development Vancouver Design Center Horizontal Display Period Start Position Register REG[28h] Default = 00000000h n bits 9-0 Horizontal Display Period Start Position Bits [9:0] These bits specify ...
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Page 102 bits 9-0 FPLINE Pulse Start Position Bits [9:0] These bits specify the start position of the horizontal sync signal pixel resolution. FPLINE Pulse Start Position in pixels = (REG[2Ch] bits 9- Note For passive ...
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Epson Research and Development Vancouver Design Center Vertical Display Period Start Position Register REG[38h] Default = 00000000h n bits 9-0 Vertical Display Period Start Position Bits [9:0] These bits specify ...
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Page 104 bits 9-0 FPFRAME Pulse Start Position Bits [9:0] These bits specify the start position of the vertical sync signal line resolution. For passive panels, these bits must be set to 00h. For TFT panels, VDPS is ...
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Epson Research and Development Vancouver Design Center 8.3.6 Picture-in-Picture Plus (PIP + PIP Display Start Address Register REG[50h] Default = 00000000h bits 16-0 PIP Display Start Address Bits [16:0] ...
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Page 106 + PIP X Positions Register REG[58h] Default = 00000000h n n Note The effect of REG[58h] through REG[5Ch] takes place only after REG[5Ch] is written and at the ...
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Epson Research and Development Vancouver Design Center + bits 9-0 PIP Window X Start Position Bits [9:0] These bits determine the X start position of the PIP panel. Due to the S1D13A04 SwivelView feature, the X start position may not ...
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Page 108 + PIP Y Positions Register REG[5Ch] Default = 00000000h n n Note 1 The effect of REG[58h] through REG[5Ch] takes place only after REG[5Ch] is written and at ...
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Epson Research and Development Vancouver Design Center + bits 9-0 PIP Window Y Start Position Bits [9:0] These bits determine the Y start position of the PIP panel. Due to the S1D13A04 SwivelView feature, the Y start position may not ...
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Page 110 8.3.7 Miscellaneous Registers Special Purpose Register REG[60h] Default = 00000000h n n bits 23-16 Reserved. These bits must be set to 0. bit 7 2D Byte Swap This ...
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Epson Research and Development Vancouver Design Center bit 5 Display Data Byte Swap The display pipe fetches 32-bit of data from the display buffer. This bit enables byte 0 and byte swapped, and byte 2 and byte ...
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Page 112 GPIO Status and Control Register REG[64h] Default = 20000000h GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 Input Input Input Input Input Enable Enable Enable Enable Enable n Note The GPIO ...
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Epson Research and Development Vancouver Design Center bit 4 GPIO4 Pin IO Status When GPIO4 is configured as an output, writing this bit drives GPIO4 high and writing this bit drives GPIO4 low. When ...
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Page 114 PWM Clock Configuration Register REG[70h] Default = 00000000h n PWM Clock Divider PWMCLK Clock Source / PWM Clock Divide Select value Note For further information ...
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Epson Research and Development Vancouver Design Center bit 3 PWM Clock Force High When this bit = 0, the PWMOUT pin function is controlled by the PWM Clock enable bit. When this bit = 1, the PWMOUT pin is forced ...
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Page 116 Scratch Pad A Register REG[80h] Default = not applicable bits 31-0 Scratch Pad A Bits [31:0] This register contains general purpose read/write bits. These bits have no effect ...
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Epson Research and Development Vancouver Design Center 8.4 USB Registers (Offset = 4000h) The S1D13A04 USB device occupies a 48 byte local register space which can be accessed by the CPU on the local host interface. To access the USB ...
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Page 118 bit 4 Endpoint 4 Stall. If this bit is set, host bulk reads from the transmit FIFO will result in a STALL acknowl- edge by the S1D13A04. No data will be returned to the USB host. bit 3 ...
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Epson Research and Development Vancouver Design Center bit 1 Endpoint 1 Interrupt Enable. When set, this bit enables an interrupt to occur when the USB Endpoint 1 Receive Mail- box registers have been written to by the USB host. Interrupt ...
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Page 120 Interrupt Enable Register 1 REG[4006h] Default = 00h bit 1 Transmit FIFO Almost Empty Interrupt Enable. When set, this bit enables an interrupt to be generated when the Transmit FIFO Almost Empty status bit ...
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Epson Research and Development Vancouver Design Center Endpoint 1 Index Register REG[4010h] Default = 00h bits 2-0 Endpoint 1 Index Register Bits [2:0]. This register determines which Endpoint 1 Receive Mailbox is accessed when the End- ...
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Page 122 Endpoint 2 Transmit Mailbox Data Register REG[401Ah] Default = 00h bits 7-0 Endpoint 2 Transmit Mailbox Data Bits [7:0]. This register is used to read or write one of the transmit mailbox registers. The ...
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Epson Research and Development Vancouver Design Center Endpoint 3 Receive FIFO Status Register REG[4024h] Default = 01h bit 4 Receive FIFO Flush Writing to this bit causes the receive FIFO to be flushed. Reading this ...
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Page 124 Endpoint 4 Transmit FIFO Count Register REG[402Ah] Default = 00h bits 7-0 Transmit FIFO Count Bits [7:0]. This register returns the number of transmit FIFO entries containing valid entries. Values range from 0 (empty) ...
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Epson Research and Development Vancouver Design Center Revision Register REG[4030h] Default = 01h bits 7-0 Chip Revision Bits [7:0]. This register returns current silicon revision number of the USB client. USB Status Register REG[4032h] Default = ...
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Page 126 Frame Counter MSB Register REG[4034h] Default = 00h Frame Counter LSB Register REG[4036h] Default = 00h bits 10-0 Frame Counter Bits [10:0] This register contains the frame counter from the ...
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Epson Research and Development Vancouver Design Center Product ID MSB REG[403Ah], Index[02h Product ID LSB REG[403Ah], Index[03h bits 15-0 Product ID Bits [15:0] These registers determine the Product ID returned in a “Get Device Descriptor” request. ...
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Page 128 USB Control REG[403Ah], Index[08h bit 0 USB String Enable. When set, this bit allows the default Vendor and Product ID String Descriptors to be returned to the host. When this bit is cleared, the string index ...
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Epson Research and Development Vancouver Design Center bit 5 EP2 Data Toggle Bit. Contains the value of the Data Toggle bit to be sent in response to the next IN token to endpoint 2 from the USB host. Note When ...
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Page 130 USBFC Input Control Register REG[4040h] Default = 0Dh 15 14 n/a USCMPEN Reserved 7 6 These bits control inputs to the USB module. bit 6 USCMPEN This bit controls the USB differential input receiver differential input ...
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Epson Research and Development Vancouver Design Center Pin Input Status / Pin Output Data Register REG[4044h] Default = depends on USB input pin state These bits can generate interrupts. bit 1 USBDETECT Input Pin Status This ...
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Page 132 Interrupt Control Status/Clear Register 0 REG[404Ah] Default = 00h 15 14 USB Host n/a Reserved Connected reads, these bits represent the interrupt status for interrupts caused by low-to-high transitions on the corresponding signals. 0 (read) ...
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Epson Research and Development Vancouver Design Center Interrupt Control Status/Clear Register 1 REG[404Ch] Default = 00h 15 14 USB Host n/a Reserved Disconnected reads, these bits represent the interrupt status for interrupts caused by high-to-low transitions on ...
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Page 134 Interrupt Control Masked Status Register 0 REG[404Eh] Default = 00h 15 14 USB Host n/a Reserved Connected 7 6 These read-only bits represent the logical AND of the corresponding Interrupt Control Status/Clear Register 0 (REG[404Ah])and the Interrupt Control ...
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Epson Research and Development Vancouver Design Center 8.5 2D Acceleration (BitBLT) Registers (Offset = 8000h) These registers control the S1D13A04 2D Acceleration engine. For detailed BitBLT programming instructions, see the S1D13A04 Programming Notes and Examples, document number X37A-G-003-xx. BitBLT Control ...
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Page 136 BitBLT Status Register REG[8004h] Default = 00000000h n/a Number of Used FIFO Entries n bits 28-24 Number of Used FIFO Entries Bits [4:0] These bits indicate the minimum ...
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Epson Research and Development Vancouver Design Center bit 0 BitBLT Busy Status This bit is a read-only status bit. When this bit = 1, the BitBLT operation is in progress. When this bit = 0, the BitBLT operation is complete. ...
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Page 138 bits 3-0 BitBLT Operation Bits [3:0] Specifies the 2D Operation to be carried out based on the following table. BitBLT Operation Bits [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Other combinations ...
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Epson Research and Development Vancouver Design Center BitBLT Source Start Address Register REG[800Ch] Default = 00000000h bits 20-0 BitBLT Source Start Address Bits [20:0] A 21-bit register that specifies the ...
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Page 140 BitBLT Memory Address Offset Register REG[8014h] Default = 00000000h n bits 10-0 BitBLT Memory Address Offset Bits [10:0] These bits are the display’s 11-bit address offset from the ...
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Epson Research and Development Vancouver Design Center BitBLT Background Color Register REG[8020h] Default = 00000000h bits 15-0 BitBLT Background Color Bits [15:0] This register specifies the BitBLT background color for ...
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Page 142 9 2D Accelerator (BitBLT) Engine 9.1 Overview The S1D13A04 is designed with a built-in 2D BitBLT engine which increases the perfor- mance of Bit Block Transfers (BitBLT). It supports 8 and 16 bit-per-pixel color depths. The BitBLT engine ...
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Epson Research and Development Vancouver Design Center 10 Frame Rate Calculation The following formula is used to calculate the display frame rate. Where: f PCLK HT VT Hardware Functional Specification Issue Date: 2003/05/01 f PCLK FrameRate = ------------------------------- - HT ...
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Page 144 11 Display Data Formats The following diagrams show the display mode data formats for a little-endian system. 1 bpp: bit Byte Byte Byte 2 16 Host Address ...
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Epson Research and Development Vancouver Design Center 12 Look-Up Table Architecture The following figures are intended to show the display data output path only. Note When Video Data Invert is enabled the video data is inverted after the Look-Up Table. ...
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Page 146 4 Bit-per-pixel Monochrome Mode Green Look-Up Table 256x6 bit-per-pixel data from Display Buffer Figure 12-3: 4 Bit-per-pixel ...
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Epson Research and Development Vancouver Design Center 16 Bit-Per-Pixel Monochrome Mode The LUT is bypassed and the green data is directly mapped for this color depth– “Display Data Formats” on page 144.. 12.2 Color Modes 1 Bit-Per-Pixel Color Red Look-Up ...
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Page 148 2 Bit-Per-Pixel Color Red Look-Up Table 256x6 Green Look-Up Table 256x6 Blue Look-Up Table 256x6 ...
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Epson Research and Development Vancouver Design Center 4 Bit-Per-Pixel Color Red Look-Up Table 256x6 Green Look-Up Table 256x6 00 01 ...
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Page 150 8 Bit-per-pixel Color Mode Red Look-Up Table 256x6 Green Look-Up Table 256x6 ...
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Epson Research and Development Vancouver Design Center 13 SwivelView™ 13.1 Concept Most computer displays are refreshed in landscape orientation – from left to right and top to bottom. Computer images are stored in the same manner. SwivelView™ is designed to ...
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Page 152 physical memory start address A SwivelView window D C 320 image seen by programmer = image in display buffer Figure 13-1: Relationship Between The Screen Image and the Image Refreshed in 90 SwivelView. 13.2.1 Register Programming Enable 90 ...
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Epson Research and Development Vancouver Design Center 13.3 180° SwivelView™ The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13A04 in the following ...
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Page 154 Line Address Offset The Main Window Line Address Offset register (REG[44h]) is based on the display width and programmed using the following formula. REG[44h] bits 9:0 13.4 270° SwivelView™ 270 SwivelView™ requires the Memory Clock (MCLK ...
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Epson Research and Development Vancouver Design Center 13.4.1 Register Programming 270 SwivelView™ Mode Enable Set SwivelView™ Mode Select bits (REG[10h] bits 17:16) to 11. Display Start Address The display refresh circuitry starts at pixel “C”, therefore the Main Window Display ...
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Page 156 14 Picture-in-Picture Plus (PIP 14.1 Concept Picture-in-Picture Plus (PIP main display window. The PIP display and is controlled through the PIP REG[5Ch]). The PIP the main window. The following diagram shows an example of a PIP registers used ...
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Epson Research and Development Vancouver Design Center 14.2 With SwivelView Enabled 14.2.1 SwivelView 90° TM 90° SwivelView + PIP window x end position (REG[58h] bits 25-16) Figure 14-2: Picture-in-Picture Plus with SwivelView 90° enabled 14.2.2 SwivelView 180° TM 180° SwivelView ...
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Page 158 14.2.3 SwivelView 270° TM 270° SwivelView + PIP window y end position (REG[5Ch] bits 25-16) + PIP window y start position (REG[5Ch] bits 9-0) + PIP window x start position (REG[58h] bits 9-0) panel’s origin Figure 14-4: Picture-in-Picture ...
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Epson Research and Development Vancouver Design Center 15 Power Save Mode A software initiated Power Save Mode is incorporated into the S1D13A04 to accommodate the need for power reduction in the hand-held devices market. This mode is enable via the ...
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Page 160 16 Mechanical Data TOP VIEW All dimensions in mm Figure 16-1: Mechanical Data PFBGA 121-pin Package S1D13A04 X37A-A-001-06 +0.30 10 -0.15 +0.10 0.45 -0.05 0. ...
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Epson Research and Development Vancouver Design Center 96 97 128 1 All dimensions in mm Figure 16-2: Mechanical Data TQFP15 128-pin Package Hardware Functional Specification Issue Date: 2003/05/01 16.0 ± 0.4 14.0 ± 0.1 65 Index 32 +0.05 0.16 -0.03 ...
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Page 162 17 References The following documents contain additional information related to the S1D13A04. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. • 13A04CFG ...
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Epson Research and Development Vancouver Design Center 18 Sales and Technical Support Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp/ Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre ...
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Page 164 S1D13A04 X37A-A-001-06 THIS PAGE LEFT BLANK Revision 6.0 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2003/05/01 ...
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Errata No. X00Z-P-001-01 Device: S1D13A03, S1D13A04, S1D13A05. Description: Setting EP4 FIFO Valid bit while NAKing an IN token. Bit 5 of REG[402Ch] indicates to the S1D13A0x controller when data in the endpoint 4 FIFO is ready to be transferred to ...
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Page 2 Corrective Action: There are two software solutions for this occurrence. Disable USB Receiver before setting the EP4 FIFO Valid bit The first solution involves disabling the USB receiver to avoid responding to an EP4 IN packet. During the ...
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S1D13A04 LCD/USB Companion Chip Programming Notes and Examples Document Number: X37A-G-003-05 Copyright © 2001, 2002 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, ...
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Page 2 S1D13A04 X37A-G-003-05 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 2002/08/21 ...
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Epson Research and Development Vancouver Design Center 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Page 4 8.2.3 SwivelView 180° ...
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Epson Research and Development Vancouver Design Center 10.4.5 Setting EP4 FIFO Valid bit while NAKing IN token . . . . . . . . . . . . . . . . . 110 11 Hardware Abstraction Layer . ...
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Page 6 S1D13A04 X37A-G-003-05 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 2002/08/21 ...
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Epson Research and Development Vancouver Design Center Table 5-1: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Epson Research and Development Vancouver Design Center Figure 4-1: Pixel Storage for 1 Bpp in One Byte of Display Buffer . . . . . . . . . . . . . . . . . . 14 Figure ...
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Page 10 S1D13A04 X37A-G-003-05 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 2002/08/21 ...
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Epson Research and Development Vancouver Design Center 1 Introduction This guide discusses programming issues and provides examples for the main features of the S1D13A04, such as SwivelView, Picture-in-Picture Plus, and the BitBLT engine. The example source code referenced in this ...
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Page 12 2 Identifying the S1D13A04 The S1D13A04 can be identified by reading the value contained in the Product Information Register (REG[00h]). To identify the S1D13A04 follow the steps below. 1. Read REG[00h]. 2. The production version of the S1D13A04 ...
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Epson Research and Development Vancouver Design Center 3 Initialization This section describes how to initialize the S1D13A04. Sample code for performing initial- ization of the S1D13A04 is provided in the file init13A04.c which is available on the internet at www.erd.epson.com. ...
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Page 14 4 Memory Models The S1D13A04 contains a display buffer of 160K bytes and supports color depths and 16 bit-per-pixel. For each color depth, the data format is packed pixel. Packed pixel data may ...
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Epson Research and Development Vancouver Design Center 4.3 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades) Bit 7 Bit 6 Pixel 0 bits 1-0 Figure 4-2: Pixel Storage for 2 Bpp in One Byte of Display Buffer At a color ...
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Page 16 4.5 Memory Organization for 8 Bpp (256 Colors/64 Gray Shades) Bit 7 Bit 6 Figure 4-4: Pixel Storage for 8 Bpp in One Byte of Display Buffer At a color depth of 8 bpp, each byte of display ...
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Epson Research and Development Vancouver Design Center 5 Look-Up Table (LUT) This section discusses programming the S1D13A04 Look-Up Table (LUT). Included is a summary of the LUT registers, recommendations for color/gray shade LUT values, and additional programming considerations. For a ...
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Page 18 5.1.2 Look-Up Table Read Registers Look-Up Table Read Register REG[1Ch] Default = 00000000h LUT Read Address (write only LUT Green Read Data This register contains the data returned ...
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Epson Research and Development Vancouver Design Center 5.2.1 Gray Shade Modes Gray shade (monochrome) modes are defined by the Color/Mono Panel Select bit (REG[0Ch] bit 6). When this bit is set to 0, the value output to the panel is ...
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Page 20 4 bpp gray shade The 4 bpp gray shade mode uses the green component of the first 16 LUT entries. The remaining indices of the LUT are unused. Table 5-4: Suggested LUT Values for 4 Bpp Gray Shade ...
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Epson Research and Development Vancouver Design Center 8 bpp gray shade When configured for 8 bpp gray shade mode, the green component of all 256 LUT entries may be used. However, this results in redundant values where each of the ...
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Page 22 16 bpp gray shade The Look-Up Table is bypassed at this color depth, therefore programming the LUT is not required. As with 8 bpp there are limitations to the colors which can be displayed. In this mode the ...
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Epson Research and Development Vancouver Design Center 4 bpp color When the S1D13A04 is configured for 4 bpp color mode the first 16 entries in the LUT are used. The remaining indices of the LUT are unused. The following table ...
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Page 24 8 bpp color When the S1D13A04 is configured for 8 bpp color mode all 256 entries in the LUT are used. The S1D13A04 LUT has six bits (64 intensities) of intensity control per primary color which is the ...
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Epson Research and Development Vancouver Design Center Table 5-9: Suggested LUT Values 8 bpp Color (Continued) Index Index ...
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Page 26 6 Power Save Mode The S1D13A04 is designed for very low-power applications. During normal operation, the internal clocks are dynamically disabled when not required. The S1D13A04 design also includes a Power Save Mode to further save power. When ...
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Epson Research and Development Vancouver Design Center 6.2 Registers 6.2.1 Power Save Mode Enable Power Save Configuration Register REG[14h] Default = 00000010h n The Power Save Mode Enable bit initiates ...
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Page 28 6.3 LCD Power Sequencing The S1D13A04 requires LCD power sequencing (the process of powering-on and powering-off the LCD panel). LCD power sequencing allows the LCD bias voltage to discharge prior to shutting down the LCD signals, preventing long ...