S1D13A04F00A Epson Electronics America Inc-Semiconductor Div, S1D13A04F00A Datasheet - Page 61
![IC LCD COMPANION 160KB 128-TQFP](/photos/7/35/73560/s1d13a04f00a_sml.jpg)
S1D13A04F00A
Manufacturer Part Number
S1D13A04F00A
Description
IC LCD COMPANION 160KB 128-TQFP
Manufacturer
Epson Electronics America Inc-Semiconductor Div
Specifications of S1D13A04F00A
Display Type
LCD
Voltage - Supply
1.8 V ~ 2.75 V
Mounting Type
Surface Mount
Package / Case
125-TQFP, 125-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Operating Temperature
-
Interface
-
Configuration
-
Digits Or Characters
-
Other names
S1D13A04F00A100
S1D13A04F00A100
S1D13A04F00A100
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6.3.2 Passive/TFT Power-Off Sequence
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
6.3.3 ‘Direct’ HR-TFT Interface Power-On/Off Sequence
Hardware Functional Specification
Issue Date: 2003/05/01
*It is recommended to use the general purpose IO pin GPIO0 to control the LCD bias power.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[14h] bit 4) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Symbol
connected.
t1
t2
(REG[A0h] bit 0)
LCD Signals***
Mode Enable**
Power Save
LCD bias deactivated to LCD signals inactive
Power Save Mode enabled to LCD signals low
GPIO0*
For ‘Direct’ HR-TFT Interface Power-On/Off sequence information, see Connecting to the
Sharp HR-TFT Panels, document number X37A-G-011-xx.
Figure 6-12: Passive/TFT Power-Off Sequence Timing
Table 6-18: Passive/TFT Power-Off Sequence Timing
Parameter
Revision 6.0
t1
Note 1
Min
0
t2
Note 1
Max
1
X37A-A-001-06
BCLK
Units
S1D13A04
Page 55
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