S1D13A04F00A Epson Electronics America Inc-Semiconductor Div, S1D13A04F00A Datasheet - Page 53

• Manufacturer Part Number: S1D13A04F00A
• Description: IC LCD COMPANION 160KB 128-TQFP
• Manufacturer: Epson Electronics America Inc-Semiconductor Div

Specifications of S1D13A04F00A

• Display Type: LCD
• Voltage - Supply: 1.8 V ~ 2.75 V
• Mounting Type: Surface Mount
• Package / Case: 125-TQFP, 125-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Operating Temperature: -
• Interface: -
• Configuration: -
• Digits Or Characters: -
• Other names: S1D13A04F00A100; S1D13A04F00A100

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 2003/05/01
Symbol
T
f
t10
t11
t12
t13
t14
t15
t16
CLK
CLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
Bus clock frequency
Bus clock period
A[16:0], M/R#, R/W#, SIZ[1:0] and CS# and AS# and DS# setup to
first CLK rising edge
CS# and AS# asserted low to DSACK1# driven
A[1:0], R/W#, SIZ[1:0], DS# asserted to D[15:0] driven
A[16:1], M/R#, R/W#, SIZ[1:0] hold from AS# rising edge
R/W#, A[1:0], SIZ[1:0] deasserted to R/W#, A[1:0], SIZ[1:0] asserted
for next cycle
CS# hold from AS# rising edge
DS# rising edge to AS# rising edge
AS# setup to CLK rising edge
DSACK1# falling edge to DS# rising edge
CLK rising edge to DSACK1# high impedance
AS# rising edge to DSACK1# rising edge
D[15:0] setup to 4th CLK rising edge after CS#=0, AS#=0, and
UDS#=0 or LDS#=0
D[15:0] hold from A[1:0], R/W#, SIZ[1:0] (write cycle)
DSACK1# falling edge to D[15:0] valid (read cycle)
DS# rising edge to D[15:0] high impedance (read cycle)
Cycle Length
Table 6-13: Motorola MC68K#2 Interface Timing
Parameter
Revision 6.0
1/f
Min
1
1
0
1
6
CLK
3
0
0
0
1
3
1
2
T
CLK
Max
50
10
8
9
3
7
- 2
X37A-A-001-06
S1D13A04
T
T
T
MHz
Unit
ns
ns
ns
ns
ns
ns
CLK
ns
ns
ns
ns
ns
CLK
ns
ns
ns
CLK
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