S1D13A04F00A Epson Electronics America Inc-Semiconductor Div, S1D13A04F00A Datasheet - Page 70
![IC LCD COMPANION 160KB 128-TQFP](/photos/7/35/73560/s1d13a04f00a_sml.jpg)
S1D13A04F00A
Manufacturer Part Number
S1D13A04F00A
Description
IC LCD COMPANION 160KB 128-TQFP
Manufacturer
Epson Electronics America Inc-Semiconductor Div
Specifications of S1D13A04F00A
Display Type
LCD
Voltage - Supply
1.8 V ~ 2.75 V
Mounting Type
Surface Mount
Package / Case
125-TQFP, 125-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Operating Temperature
-
Interface
-
Configuration
-
Digits Or Characters
-
Other names
S1D13A04F00A100
S1D13A04F00A100
S1D13A04F00A100
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Part Number:
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Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
Company:
Part Number:
S1D13A04F00A1
Manufacturer:
EPSON
Quantity:
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S1D13A04F00A1
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Part Number:
S1D13A04F00A100
Manufacturer:
OSRAM
Quantity:
4 600
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Page 64
6.4.4 Single Color 4-Bit Panel Timing
VDP
VNDP
HDP
HNDP
S1D13A04
X37A-A-001-06
- FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Notes:
DRDY (MOD)
DRDY (MOD)
= Vertical Display Period
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
FPDAT[7:4]
FPFRAME
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPLINE
FPLINE
Invalid
Invalid
Invalid
Invalid
Invalid
.5Ts
1-R1
1-B1
1-R2
1-G1
Figure 6-19: Single Color 4-Bit Panel Timing
.5Ts
.5Ts
1-G2
1-B2
1-R3
1-G3
LINE1
.5Ts
.5Ts
1-B3
1-R4
1-G4
1-B4
.5Ts
LINE2
.5Ts
.5Ts
LINE3
.5Ts
.5Ts
Revision 6.0
.5Ts
LINE4
VDP
2.5Ts
HDP
.5Ts
.5Ts
.5Ts
LINE239 LINE240
.5Ts
.5Ts
.5Ts
1-B319
1-R320
1-G320
1-B320
VNDP
Epson Research and Development
Invalid
Hardware Functional Specification
Invalid
Invalid
Invalid
Invalid
HNDP
Vancouver Design Center
LINE1
Issue Date: 2003/05/01
.5Ts
LINE2
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