S1D13A04F00A Epson Electronics America Inc-Semiconductor Div, S1D13A04F00A Datasheet - Page 108

• Manufacturer Part Number: S1D13A04F00A
• Description: IC LCD COMPANION 160KB 128-TQFP
• Manufacturer: Epson Electronics America Inc-Semiconductor Div

Specifications of S1D13A04F00A

• Display Type: LCD
• Voltage - Supply: 1.8 V ~ 2.75 V
• Mounting Type: Surface Mount
• Package / Case: 125-TQFP, 125-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Operating Temperature: -
• Interface: -
• Configuration: -
• Digits Or Characters: -
• Other names: S1D13A04F00A100; S1D13A04F00A100

Page 102
bits 9-0
bits 9-0
bits 9-0
S1D13A04
X37A-A-001-06
Vertical Total Register
REG[30h]
Vertical Display Period Register
REG[34h]
31
15
31
15
30
14
30
14
29
13
29
13
n/a
n/a
Default = 00000000h
Default = 00000000h
Note
Note
Note
Note
28
12
28
12
FPLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in 1 pixel resolution.
FPLINE Pulse Start Position in pixels = (REG[2Ch] bits 9-0) + 1
Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period. The
maximum Vertical Total is 1024 lines.
REG[30h] bits 9:0 = Vertical Total in number of lines - 1
Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The
Vertical Display period should be less than the Vertical Total to allow for a sufficient
Vertical Non-Display period.
REG[34h] bits 9:0 = Vertical Display Period in number of lines - 1
For passive panels, these bits must be programmed such that the following formula is
valid.
See Section 6.4, “Display Interface” on page 56.
1
2
1
2
This register must be programmed such that the following formula is valid.
See Section 6.4, “Display Interface” on page 56.
This register must be programmed such that the following formula is valid.
See Section 6.4, “Display Interface” on page 56.
VDPS + VDP
HPW + HPS < HT
VDPS + VDP < VT
27
11
27
11
26
10
26
10
VT
25
25
9
9
24
24
8
8
Revision 6.0
n/a
n/a
23
23
7
7
22
22
6
6
Vertical Display Period bits 9-0
Vertical Total bits 9-0
21
21
5
5
20
20
4
4
Epson Research and Development
Hardware Functional Specification
19
19
3
3
Vancouver Design Center
Issue Date: 2003/05/01
18
18
2
2
Read/Write
Read/Write
17
17
1
1
16
16
0
0