ATAVRMC321 Atmel, ATAVRMC321 Datasheet - Page 130

• Manufacturer Part Number: ATAVRMC321
• Description: KIT EVAL MOTOR CTRL LOW COST
• Manufacturer: Atmel
• Series: AVR®r

Specifications of ATAVRMC321

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATtinyx61
• Primary Attributes: 3-Ph BLDC, Brushed DC, Stepper Motor- Controller Board
• Secondary Attributes: Includes ATAVRMC300 Power Driver Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ATtiny261/461/861
Figure 13-4. Two-wire Mode Operation, Simplified Diagram
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-
bus, must be implemented to control the data flow.
Figure 13-5. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram
SDA
SCL
1. The start condition is generated by the master by forcing the SDA low line while keep-
2. In addition, the start detector will hold the SCL line low after the master has forced a
ing the SCL line high (A). SDA can be forced low either by writing a zero to bit 7 of the
USI Data Register, or by setting the corresponding bit in the PORTA register to zero.
Note that the Data Direction Register bit must be set to one for the output to be
enabled. The start detector logic of the slave device (see
detects the start condition and sets the USISIF Flag. The flag can generate an interrupt
if necessary.
negative edge on this line (B). This allows the slave to wake up from sleep or complete
other tasks before setting up the USI Data Register to receive the address. This is done
by clearing the start condition flag and resetting the counter.
SLAVE
MASTER
A B
S
Bit7
Bit7
Bit6
Bit6
C
ADDRESS
1 - 7
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
R/W
(Figure
8
Bit2
Bit2
D
Bit1
Bit1
13-5), a bus transfer involves the following steps:
ACK
9
Bit0
Bit0
E
DATA
1 - 8
Two-wire Clock
Control Unit
ACK
9
PORTxn
Figure 13-6 on page
HOLD
SCL
DATA
1 - 8
SDA
SCL
SDA
SCL
ACK
9
VCC
2588E–AVR–08/10
131)
P
F