ATAVRMC321 Atmel, ATAVRMC321 Datasheet - Page 71

• Manufacturer Part Number: ATAVRMC321
• Description: KIT EVAL MOTOR CTRL LOW COST
• Manufacturer: Atmel
• Series: AVR®r

Specifications of ATAVRMC321

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATtinyx61
• Primary Attributes: 3-Ph BLDC, Brushed DC, Stepper Motor- Controller Board
• Secondary Attributes: Includes ATAVRMC300 Power Driver Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11. Timer/Counter0
11.1
11.2
11.2.1
2588E–AVR–08/10
Features
Overview
Registers
•
•
•
•
•
Timer/Counter0 is a general purpose 8/16-bit Timer/Counter module, with two/one Output Com-
pare units and Input Capture feature.
The general operation of Timer/Counter0 is described in 8/16-bit mode. A simplified block dia-
gram of the 8/16-bit Timer/Counter is shown in
including I/O bits and I/O pins, are shown in bold. For actual placement of I/O pins, refer to
out ATtiny261/461/861 and ATtiny261V/461V/861V” on page
bit locations are listed in the
Figure 11-1. 8-/16-bit Timer/Counter Block Diagram
The Timer/Counter0 Low Byte Register (TCNT0L) and Output Compare Registers (OCR0A and
OCR0B) are 8-bit registers. Interrupt request (abbreviated Int.Req. in
Clear Timer on Compare Match (Auto Reload)
One Input Capture unit
Four Independent Interrupt Sources (TOV0, OCF0A, OCF0B, ICF0)
8-bit Mode with Two Independent Output Compare Units
16-bit Mode with One Independent Output Compare Unit
TCCRnA
TCNTnH
OCRnB
=
Timer/Counter
“Register Description” on page
Direction
Count
Clear
TCNTnL
TCCRnB
OCRnA
=
Control Logic
TOP
Figure
Detector
Edge
clk
=
Tn
11-1. CPU accessible I/O Registers,
84.
2. Device-specific I/O Register and
Canceler
Fixed TOP value
( From Prescaler )
Noise
Figure
Clock Select
Detector
Edge
TOVn (Int. Req.)
11-1) signals are all
Comparator Ouput )
OCnA (Int. Req.)
OCnB (Int. Req.)
ICFn (Int. Req.)
( From Analog
ICPn
Tn
“Pin-
71