ATAVRMC321 Atmel, ATAVRMC321 Datasheet - Page 73

• Manufacturer Part Number: ATAVRMC321
• Description: KIT EVAL MOTOR CTRL LOW COST
• Manufacturer: Atmel
• Series: AVR®r

Specifications of ATAVRMC321

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATtinyx61
• Primary Attributes: 3-Ph BLDC, Brushed DC, Stepper Motor- Controller Board
• Secondary Attributes: Includes ATAVRMC300 Power Driver Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.1.1
11.3.2
2588E–AVR–08/10
External Clock Source
Prescaler Reset
Figure 11-2. Prescaler for Timer/Counter0
Note:
The prescaled clock has a frequency of f
Table 11-4 on page 85
The prescaler is free running, i.e. it operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state
of the prescaler will have implications for situations where a prescaled clock is used. One exam-
ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >
CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count
occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64,
256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to
program execution.
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the T0 synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
The edge detector generates one clk
= 6) edge it detects. See
PSR0
clk
T0
I/O
1. The synchronization logic on the input pins (
Synchronization
for details.
Table 11-4 on page 85
Clear
T
0
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
CLK_I/O
/8, f
for details.
T0)
CLK_I/O
is shown in
/64, f
clk
I/O
CLK_I/O
). The latch is transparent in the
Figure
Figure 11-3
/256, or f
11-3.
clk
T0
shows a functional
CLK_I/O
/1024. See
T0
). The
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