ATAVRMC321 Atmel, ATAVRMC321 Datasheet - Page 145

• Manufacturer Part Number: ATAVRMC321
• Description: KIT EVAL MOTOR CTRL LOW COST
• Manufacturer: Atmel
• Series: AVR®r

Specifications of ATAVRMC321

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATtinyx61
• Primary Attributes: 3-Ph BLDC, Brushed DC, Stepper Motor- Controller Board
• Secondary Attributes: Includes ATAVRMC300 Power Driver Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5
2588E–AVR–08/10
Prescaling and Conversion Timing
conversion will not be started. If another positive edge occurs on the trigger signal during con-
version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific
interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus
be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to
trigger a new conversion at the next interrupt event.
Figure 15-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
See
Figure 15-3 on page
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADTS[2:0]
146.
DETECTOR
EDGE
ADATE
START
CONVERSION
PRESCALER
LOGIC
CLK
ADC
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