EVAL-ADUC831QSZ Analog Devices Inc, EVAL-ADUC831QSZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-ADUC831QSZ
• Description: KIT DEV FOR ADUC831 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC831QSZ

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: 8051
• Silicon Core Number: ADuC831
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC831
• Lead Free Status / Rohs Status: Compliant
• Other names: EVAL-ADUC831QS; EVAL-ADUC831QS

ADCCON3 – (ADC Control SFR #3)
The ADCCON3 register controls the operation of various calibra-
tion modes as well as giving an indication of ADC busy status.
SFR Address:
SFR Power-On Default Value:
Bit Addressable:
Bit
ADCCON3.7 BUSY
ADCCON3.6 GNCLD
ADCCON3.5 AVGS1
ADCCON3.4 AVGS0
ADCCON3.3 RSVD
ADCCON3.2 RSVD
ADCCON3.1 TYPICAL
ADCCON3.0 SCAL
REV. 0
Name
Description
The ADC Busy Status Bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or
calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration.
Gain Calibration Disable Bit
Set to “0” to Enable Gain Calibration.
Set to “1” to Disable Gain Calibration.
Number of Averages Selection Bits
This bit selects the number of ADC readings averaged during a calibration cycle.
AVGS1
0
0
1
1
Reserved. This bit should always be written as “0.”
This bit should always be written as “1” by the user when performing calibration.
Calibration Type Select Bit.
This bit selects between Offset (zero-scale) and gain (full-scale) calibration.
Set to 0 for Offset Calibration.
Set to 1 for Gain Calibration.
Start Calibration Cycle Bit.
When set, this bit starts the selected calibration cycle. It is automatically cleared when the calibration
cycle is completed.
F5H
00H
NO
AVGS0
0
1
0
1
Table V. ADCCON3 SFR Bit Designations
Number of Averages
15
1
31
63
–21–
ADuC831