EVAL-ADUC831QSZ Analog Devices Inc, EVAL-ADUC831QSZ Datasheet - Page 51

• Manufacturer Part Number: EVAL-ADUC831QSZ
• Description: KIT DEV FOR ADUC831 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC831QSZ

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: 8051
• Silicon Core Number: ADuC831
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC831
• Lead Free Status / Rohs Status: Compliant
• Other names: EVAL-ADUC831QS; EVAL-ADUC831QS

TCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
*These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as
independent registers or combined to be a single 16-bit register,
depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8CH, 8AH respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8DH, 8BH respectively.
REV. 0
Name
TF1
TR1
TF0
TR0
IE1*
IT1*
IE0*
IT0*
Timer/Counter 0 and 1 Control Register
88H
00H
Yes
Description
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit.
Set by user to turn on Timer/Counter 1.
Cleared by user to turn off Timer/Counter 1.
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by user to turn on Timer/Counter 0.
Cleared by user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt Pin INT1,
depending on bit IT1 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was
transition-activated. If level-activated, the external requesting source controls the request flag,
rather than the on-chip hardware.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt Pin INT0,
depending on bit IT0 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt
was transition-activated. If level-activated, the external requesting source controls the request
flag, rather than the on-chip hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
Table XX. TCON SFR Bit Designations
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ADuC831