MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 110

• Manufacturer Part Number: MC9S12C128CFUE
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4000 B
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 1
• Operating Supply Voltage: - 0.3 V to + 6.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3 Module Mapping Control (MMCV4) Block Description
3.1.1
3.1.2
Some of the registers operate differently depending on the mode of operation (i.e., normal expanded wide,
special single chip, etc.). This is best understood from the register descriptions.
3.2
All interfacing with the MMC sub-block is done within the core, it has no external signals.
3.3
A summary of the registers associated with the MMC sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
3.3.1
110
•
•
•
•
•
•
•
•
•
•
•
Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM)
memory blocks and associated registers
Memory mapping control and selection based upon address decode and system operating mode
Core address bus control
Core data bus control and multiplexing
Core security state decoding
Emulation chip select signal generation (ECS)
External chip select signal generation (XCS)
Internal memory expansion
External stretch and ROM mapping control functions via the MISC register
Reserved registers for test purposes
Configurable system memory options defined at integration of core into the system-on-a-chip
(SoC).
External Signal Description
Memory Map and Register Definition
Address
0x0010
0x0011
0x0012
0x0013
0x0014
Offset
Features
Modes of Operation
Module Memory Map
.
.
Initialization of Internal RAM Position Register (INITRM)
Initialization of Internal Registers Position Register (INITRG)
Initialization of Internal EEPROM Position Register (INITEE)
Miscellaneous System Control Register (MISC)
Reserved
MC9S12C-Family / MC9S12GC-Family
Table 3-1. MMC Memory Map
Rev 01.24
Register
.
.
Figure
3-2. Detailed
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
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